Single Event Upset Detection and Correction in Virtex-4 and Virtex-5 FPGAs.
Bradley F. DuttonCharles E. StroudPublished in: CATA (2009)
Keyphrases
- hardware implementation
- field programmable gate array
- reconfigurable hardware
- event detection
- low cost
- fpga device
- efficient implementation
- hardware software
- detection algorithm
- detection rate
- image processing
- parallel computing
- signal processing
- hardware architecture
- hardware design
- data sets
- detection method
- false positives
- object detection
- neural network
- embedded systems
- soccer video
- error correction
- genetic algorithm
- event recognition
- computer vision
- image processing algorithms
- detection accuracy
- false alarms
- real time
- anomaly detection