Mahesh A. Iyer

Publication Activity (10 Years)

Years Active: 1992-2024
Publications (10 Years): 13

Top Topics

Dynamic Programming

Reinforcement Learning

Top Venues

Publications

Yuan Meng, Michael Kinsner, Deshanand P. Singh, Mahesh A. Iyer, Viktor K. Prasanna
PEARL: Enabling Portable, Productive, and High-Performance Deep Reinforcement Learning using Heterogeneous Platforms. CF (2024)
Rachel Selina Rajarathnam, Zixuan Jiang, Mahesh A. Iyer, David Z. Pan
DREAMPlaceFPGA-PL: An Open-Source GPU-Accelerated Packer-Legalizer for Heterogeneous FPGAs. ISPD (2023)
Rachel Selina Rajarathnam, Mohamed Baker Alawieh, Zixuan Jiang, Mahesh A. Iyer, David Z. Pan
DREAMPlaceFPGA: An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit. ASP-DAC (2022)
Mahesh A. Iyer
Symbiosis in Action: Reconfigurable Architectures and EDA. FPGA (2020)
Mohamed Baker Alawieh, Wuxi Li, Yibo Lin, Love Singhal, Mahesh A. Iyer, David Z. Pan
High-Definition Routing Congestion Prediction for Large-Scale FPGAs. ASP-DAC (2020)
Ilya K. Ganusov, Mahesh A. Iyer, Ning Cheng, Alon Meisler
Agilex™ Generation of Intel® FPGAs. Hot Chips Symposium (2020)
Shounak Dhar, Love Singhal, Mahesh A. Iyer, David Z. Pan
A shape-driven spreading algorithm using linear programming for global placement. ASP-DAC (2019)
Shounak Dhar, Love Singhal, Mahesh A. Iyer, David Z. Pan
FPGA Accelerated FPGA Placement. FPL (2019)
Shounak Dhar, Love Singhal, Mahesh A. Iyer, David Z. Pan
FPGA-Accelerated Spreading for Global Placement. HPEC (2019)
Love Singhal, Mahesh A. Iyer, Saurabh N. Adya
LSC: A Large-Scale Consensus-Based Clustering Algorithm for High-Performance FPGAs. DAC (2017)
Mahesh A. Iyer
CAD Opportunities with Hyper-Pipelining. ISPD (2017)
Shounak Dhar, Mahesh A. Iyer, Saurabh N. Adya, Love Singhal, Nikolay Rubanov, David Z. Pan
An Effective Timing-Driven Detailed Placement Algorithm for FPGAs. ISPD (2017)
Shounak Dhar, Saurabh N. Adya, Love Singhal, Mahesh A. Iyer, David Z. Pan
Detailed placement for modern FPGAs using 2D dynamic programming. ICCAD (2016)
Prashant Saxena, Vishal Khandelwal, Changge Qiao, Pei-Hsin Ho, J.-C. Lin, Mahesh A. Iyer
On improving optimization effectiveness in interconnect-driven physical synthesis. ISPD (2009)
Mahesh A. Iyer
A Robust and Scalable Technique for the Constraints Solving Problem in High-Level Verification. MTV (2003)
Mahesh A. Iyer
Race: A Word-Level ATPG-Based Constraints Solver System For Smart Random Simulation. ITC (2003)
David E. Long, Mahesh A. Iyer, Miron Abramovici
FILL and FUNI: algorithms to identify illegal states and sequentially untestable faults. ACM Trans. Design Autom. Electr. Syst. 5 (3) (2000)
Narendra V. Shenoy, Mahesh A. Iyer, Robert F. Damiano, Kevin Harer, Hi-Keung Tony Ma, Paul Thilking
A Robust Solution to the Timing Convergence Problem in High-Performance Design. ICCD (1999)
Mahesh A. Iyer
High Time For High Level ATPG. ITC (1999)
Leon Stok, Andrew J. Sullivan, Mahesh A. Iyer
Wavefront Technology Mapping. DATE (1999)
Mahesh A. Iyer, David E. Long, Miron Abramovici
Surprises in Sequential Redundancy Identification. ED&TC (1996)
Mahesh A. Iyer, David E. Long, Miron Abramovici
Identifying Sequential Redundancies Without Search. DAC (1996)
Mahesh A. Iyer, Miron Abramovici
FIRE: a fault-independent combinational redundancy identification algorithm. IEEE Trans. Very Large Scale Integr. Syst. 4 (2) (1996)
David E. Long, Mahesh A. Iyer, Miron Abramovici
Identifying sequentially untestable faults using illegal states. VTS (1995)
Srimat T. Chakradhar, Mahesh A. Iyer, Vishwani D. Agrawal
Energy models for delay testing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14 (6) (1995)
Mahesh A. Iyer, Miron Abramovici
Sequentially Untestable Faults Identified Without Search ("Simple Implications Beat Exhaustive Search!"). ITC (1994)
Mahesh A. Iyer, Miron Abramovici
Low-Cost Redundancy Identification for Combinatorial Circuits. VLSI Design (1994)
Miron Abramovici, Mahesh A. Iyer
One-Pass Redundancy Identification and Removal. ITC (1992)