Narendra V. Shenoy

Publication Activity (10 Years)

Years Active: 1990-2008
Publications (10 Years): 0

Publications

Shabbir H. Batterywala, Sambuddha Bhattacharya, Subramanian Rajagopalan, Hi-Keung Tony Ma, Narendra V. Shenoy
Cell Swapping Based Migration Methodology for Analog and Custom Layouts. ISQED (2008)
Sambuddha Bhattacharya, Shabbir H. Batterywala, Subramanian Rajagopalan, Hi-Keung Tony Ma, Narendra V. Shenoy
On Efficient and Robust Constraint Generation for Practical Layout Legalization. ISQED (2008)
Debjit Sinha, Hai Zhou, Narendra V. Shenoy
Advances in Computation of the Maximum of a Set of Gaussian Random Variables. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (8) (2007)
Debjit Sinha, Jianfeng Luo, Subramanian Rajagopalan, Shabbir H. Batterywala, Narendra V. Shenoy, Hai Zhou
Impact of Modern Process Technologies on the Electrical Parameters of Interconnects. VLSI Design (2007)
Debjit Sinha, Hai Zhou, Narendra V. Shenoy
Advances in Computation of the Maximum of a Set of Random Variables. ISQED (2006)
Debjit Sinha, Narendra V. Shenoy, Hai Zhou
Statistical Timing Yield Optimization by Gate Sizing. IEEE Trans. Very Large Scale Integr. Syst. 14 (10) (2006)
Debjit Sinha, Narendra V. Shenoy, Hai Zhou
Statistical gate sizing for timing yield optimization. ICCAD (2005)
Shabbir H. Batterywala, Narendra V. Shenoy
Computing Silent Gate Models for Noise Analysis from Slew and Delay Tables. VLSI Design (2004)
Narendra V. Shenoy, Jamil Kawa, Raul Camposano
Design automation for mask programmable fabrics. DAC (2004)
Chi-Foon Chan, Deirdre Hanford, Jian Yue Pan, Narendra V. Shenoy, Mahesh Mehendale, A. Vasudevan, Shaojun Wei
Emerging markets: design goes global. DAC (2003)
Shabbir H. Batterywala, Narendra V. Shenoy
A Method to Estimate Slew and Delay in Coupled Digital Circuits. VLSI Design (2003)
Narendra V. Shenoy, William Nicholls
An efficient routing database. DAC (2002)
Shabbir H. Batterywala, Narendra V. Shenoy, William Nicholls, Hai Zhou
Track assignment: a desirable intermediate step between global routing and detailed routing. ICCAD (2002)
Stan Y. Liao, Narendra V. Shenoy, William Nicholls
An Efficient External-Memory Implementation of Region Query with Application to Area Routing. ICCD (2002)
Hai Zhou, Narendra V. Shenoy, William Nicholls
Efficient minimum spanning tree construction without Delaunay triangulation. Inf. Process. Lett. 81 (5) (2002)
Hai Zhou, Narendra V. Shenoy, William Nicholls
Timing Analysis with Crosstalk as Fixpoints on Complete Lattice. DAC (2001)
Hai Zhou, Narendra V. Shenoy, William Nicholls
Efficient minimum spanning tree construction without Delaunay triangulation. ASP-DAC (2001)
Narendra V. Shenoy, Mahesh A. Iyer, Robert F. Damiano, Kevin Harer, Hi-Keung Tony Ma, Paul Thilking
A Robust Solution to the Timing Convergence Problem in High-Performance Design. ICCD (1999)
Ramsey W. Haddad, Lukas P. P. P. van Ginneken, Narendra V. Shenoy
Discrete Drive Selection for Continuous Sizing. ICCD (1997)
Narendra V. Shenoy
Retiming: Theory and practice. Integr. 22 (1-2) (1997)
Kurt Keutzer, A. Richard Newton, Narendra V. Shenoy
The future of logic synthesis and physical design in deep-submicron process geometries. ISPD (1997)
Ralph H. J. M. Otten, Lukas P. P. P. van Ginneken, Narendra V. Shenoy
Embedded tutorial: Speed - new paradigms in design for performance. ICCAD (1996)
Alexander Saldanha, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
Functional clock schedule optimization. VLSI Design (1995)
Narendra V. Shenoy, Richard L. Rudell
Efficient implementation of retiming. ICCAD (1994)
Luciano Lavagno, Narendra V. Shenoy, Alberto L. Sangiovanni-Vincentelli
Linear programming for hazard elimination in asynchronous circuits. J. VLSI Signal Process. 7 (1-2) (1994)
Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
Minimum padding to satisfy short path constraints. ICCAD (1993)
Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
Resynthesis of Multi-Phase Pipelines. DAC (1993)
Masamichi Kawarabayashi, Narendra V. Shenoy, Alberto L. Sangiovanni-Vincentelli
A Verification Technique for Gated Clock. DAC (1993)
Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
Graph algorithms for clock schedule optimization. ICCAD (1992)
Thomas G. Szymanski, Narendra V. Shenoy
Verifying clock schedules. ICCAD (1992)
Narendra V. Shenoy, Kanwar Jit Singh, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
On the Temporal Equivalence of Sequential Circuits. DAC (1992)
Rajeev Murgai, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
Improved Logic Synthesis Algorithms for Table Look Up Architectures. ICCAD (1991)
Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
Retiming of Circuits with Single Phase Transparent Latches. ICCD (1991)
Rajeev Murgai, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
Performance Directed Synthesis for Table Look Up Programmable Gate Arrays. ICCAD (1991)
Rajeev Murgai, Yoshihito Nishizaki, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
Logic Synthesis for Programmable Gate Arrays. DAC (1990)