Mahesh Mehendale

Publication Activity (10 Years)

Years Active: 1989-2024
Publications (10 Years): 14

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Publications

Adithya Krishna, Srikanth Rohit Nudurupati, Chandana D. G, Pritesh Dwivedi, André van Schaik, Mahesh Mehendale, Chetan Singh Thakur
RAMAN: A Reconfigurable and Sparse tinyML Accelerator for Inference on Edge. IEEE Internet Things J. 11 (14) (2024)
Adithya Krishna, Ashwin Rajesh, Hitesh Pavan Oleti, Anand Chauhan, Shankaranarayanan H, André van Schaik, Mahesh Mehendale, Chetan Singh Thakur
Live Demonstration: Real-time audio and visual inference on the RAMAN TinyML accelerator. ISCAS (2024)
Adithya Krishna, Hitesh Pavan Oleti, Anand Chauhan, H. Shankaranarayanan, André van Schaik, Mahesh Mehendale, Chetan Singh Thakur
Live Demonstration: Audio Inference using Neuromorphic Cochlea on RAMAN Accelerator. BioCAS (2023)
Adithya Krishna, Vignesh Ramanathan, Satyapreet Singh Yadav, Sahil Shah, André van Schaik, Mahesh Mehendale, Chetan Singh Thakur
A Sparsity-driven tinyML Accelerator for Decoding Hand Kinematics in Brain-Computer Interfaces. BioCAS (2023)
Adithya Krishna, Srikanth Rohit Nudurupati, Chandana D. G, Pritesh Dwivedi, André van Schaik, Mahesh Mehendale, Chetan Singh Thakur
RAMAN: A Re-configurable and Sparse tinyML Accelerator for Inference on Edge. CoRR (2023)
Avishek Biswas, Hetul Sanghvi, Mahesh Mehendale, G. Preet
An area-efficient 6T-SRAM based Compute-In-Memory architecture with reconfigurable SAR ADCs for energy-efficient deep neural networks in edge ML applications. CICC (2022)
Vipul Singhal, Rajat Chauhan, Vinod Menezes, R. R. Manikandan, Raveesh Magod, Mahesh Mehendale, Anantha P. Chandrakasan
150nA IQ, Quad Input - Quad Output, Intelligent Integrated Power Management for IoT Applications. VLSI Design (2021)
Hassan Dbouk, Hetul Sanghvi, Mahesh Mehendale, Naresh R. Shanbhag
DBQ: A Differentiable Branch Quantizer for Lightweight Deep Neural Networks. CoRR (2020)
Hassan Dbouk, Hetul Sanghvi, Mahesh Mehendale, Naresh R. Shanbhag
DBQ: A Differentiable Branch Quantizer for Lightweight Deep Neural Networks. ECCV (27) (2020)
R. R. Manikandan, Vipul Kumar Singhal, Rajat Chauhan, Vinod Menezes, Mahesh Mehendale
A 1.2 pJ/cycle KHz Timer Circuit for Heavily Duty-Cycled Systems. VLSI Design (2018)
Takashi Hashimoto, Mahesh Mehendale, Byeong-Gyu Nam
Session 14 overview: Deep-learning processors. ISSCC (2017)
Mahesh Mehendale, Luke Shin
Session 4 overview: Digital processors. ISSCC (2016)
Vivek De, Kerry Bernstein, Takefumi Yoshikawa, Yusuf Leblebici, Marian Verhelst, Mahesh Mehendale, Makoto Nagata
F1: Designing secure systems: Manufacturing, circuits and architectures. ISSCC (2016)
Nagendra Gulur, R. Govindarajan, Mahesh Mehendale
MicroRefresh: Minimizing Refresh Overhead in DRAM Caches. MEMSYS (2016)
Dipan Kumar Mandal, Mihir Mody, Mahesh Mehendale, Naresh Yadav, Ghone Chaitanya, Piyali Goswami, Hetul Sanghvi, Niraj Nandan
Accelerating H.264/HEVC video slice processing using application specific instruction set processor. ICCE (2015)
Nagendra Dwarakanath Gulur, Mahesh Mehendale, Ramaswamy Govindarajan
A Comprehensive Analytical Performance Model of DRAM Caches. ICPE (2015)
Vipul Kumar Singhal, Vinod Menezes, Srinivasa Chakravarthy, Mahesh Mehendale
8.3 A 10.5μA/MHz at 16MHz single-cycle non-volatile memory access microcontroller with full state retention at 108nA in a 90nm process. ISSCC (2015)
Nagendra Dwarakanath Gulur, Mahesh Mehendale, R. Manikantan, R. Govindarajan
Bi-Modal DRAM Cache: Improving Hit Rate, Hit Latency and Bandwidth. MICRO (2014)
Nagendra Gulur, Mahesh Mehendale, Raman Manikantan, Ramaswamy Govindarajan
ANATOMY: an analytical model of memory system performance. SIGMETRICS (2014)
Hetul Sanghvi, Mihir N. Mody, Niraj Nandan, Mahesh Mehendale, Subrangshu Das, Dipan Kumar Mandal, Pavan Shastry
A 28nm programmable and low power ultra-HD video codec engine. ISCAS (2014)
Hetul Sanghvi, Mihir N. Mody, Niraj Nandan, Mahesh Mehendale, Subrangshu Das, Dipan Kumar Mandal, Nainala Vyagrheswarudu, Vijayavardhan Baireddy, Pavan Shastry
A monolithic programmable Ultra-HD video codec engine. ICASSP (2014)
Nagendra Dwarakanath Gulur, R. Manikantan, Mahesh Mehendale, R. Govindarajan
Multiple sub-row buffers in DRAM: unlocking performance and energy improvement opportunities. ICS (2012)
Mahesh Mehendale, Subrangshu Das, Mohit Sharma, Mihir N. Mody, Ratna Reddy, Joseph Meehan, Hideo Tamama, Brian Carlson, Mike Polley
A true multistandard, programmable, low-power, full HD video-codec engine for smartphone SoC. ISSCC (2012)
Ajit Gupte, Bharadwaj Amrutur, Mahesh Mehendale, Ajit V. Rao, Madhukar Budagavi
Memory Bandwidth and Power Reduction Using Lossy Reference Frame Compression in Video Encoding. IEEE Trans. Circuits Syst. Video Technol. 21 (2) (2011)
Nagendra Dwarakanath Gulur, R. Manikantan, R. Govindarajan, Mahesh Mehendale
Row-Buffer Reorganization: Simultaneously Improving Performance and Reducing Energy in DRAMs. PACT (2011)
Subash Chandar G., Mahesh Mehendale, R. Govindarajan
Area and Power Reduction of Embedded DSP Systems using Instruction Compression and Re-configurable Encoding. J. VLSI Signal Process. 44 (3) (2006)
Mahesh Mehendale
SoC - The Road Ahead. VLSI Design (2006)
Mahesh Mehendale
Challenges in the Design of Embedded Real-time DSP SoCs. VLSI Design (2004)
Chi-Foon Chan, Deirdre Hanford, Jian Yue Pan, Narendra V. Shenoy, Mahesh Mehendale, A. Vasudevan, Shaojun Wei
Emerging markets: design goes global. DAC (2003)
Amitabh Menon, S. K. Nandy, Mahesh Mehendale
Multivoltage scheduling with voltage-partitioned variable storage. ISLPED (2003)
Ajit Gupte, Mahesh Mehendale, Ramesh Ramamritham, Deepa Nair
Performance Considerations in Embedded DSP based System-On-a-Chip Designs. VLSI Design (2001)
Vikas Agrawal, Anand Pande, Mahesh Mehendale
High Level Synthesis Of Multi-Precision Data Flow Graphs. VLSI Design (2001)
Mahesh Mehendale, Santhosh Kumar Amanna
Functional Verification of Programmable DSP Cores. VLSI Design (2001)
Subash Chandar G., Mahesh Mehendale, R. Govindarajan
Area and Power Reduction of Embedded DSP Systems using Instruction Compression and Re-Configurable Encoding. ICCAD (2001)
M. N. Mahesh, Mahesh Mehendale
Low Power Realization of Residue Number System Based FIR Filters. VLSI Design (2000)
Mahesh Mehendale, Sunil D. Sherlekar
Power Reduction Techniques for Portable DSP Applications. VLSI Design (2000)
Sunsil Sinha, Mahesh Mehendale
Integrated IC design approach based on software engineering paradigm. CICC (1999)
M. N. Mahesh, Satrajit Gupta, Mahesh Mehendale
Improving Area Efficiency of Residue Number System based Implementation of DSP Algorithms. VLSI Design (1999)
M. N. Mahesh, Mahesh Mehendale
Improving performance of high precision signal processing algorithms on programmable DSPs. ISCAS (3) (1999)
Mahesh Mehendale, Sunil D. Sherlekar
Low Power Code Generation of Multiplication-free Linear Transforms. VLSI Design (1999)
Mahesh Mehendale, Somdipta Basu Roy, Sunil D. Sherlekar, G. Venkatesh
Coefficient Transformations for Area-Efficient Implementation of Multiplier-less FIR Filters. VLSI Design (1998)
Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh
Algorithmic and Architectural Transformations for Low Power Realization of FIR Filters. VLSI Design (1998)
Mahesh Mehendale, Amit Sinha, Sunil D. Sherlekar
Low Power Realization of FIR Filters Implemented using Distributed Arithmetic. ASP-DAC (1998)
Amit Sinha, Mahesh Mehendale
mproving Area Efficiency of FIR Filters Implemented Using Distributed Arithmetic. VLSI Design (1998)
Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh
Extensions to Programmable DSP architectures for Reduced Power Dissipation. VLSI Design (1998)
Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh
Low-power realization of FIR filters on programmable DSPs. IEEE Trans. Very Large Scale Integr. Syst. 6 (4) (1998)
Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh
Area-Delay Tradeoff in Distributed Arithmetic Based Implementation of FIR Filters. VLSI Design (1997)
Mahesh Mehendale, G. Venkatesh, Sunil D. Sherlekar
Optimized Code Generation of Multiplication-free Linear Transforms. DAC (1996)
Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh
Low power realization of FIR filters using multirate architectures. VLSI Design (1996)
Mahesh Mehendale, M. K. Ram Prasad
AATMA: an algorithm for technology mapping for antifuse-based FPGAs. VLSI Design (1995)
Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh
Techniques for low power realization for FIR filters. ASP-DAC (1995)
Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh
Synthesis of multiplier-less FIR filters with minimum number of additions. ICCAD (1995)
Mahesh Mehendale, Biswadip Mitra
An Integrated Approach to State Assignment and Sequential Element Selection for FSM Synthesis. VLSI Design (1994)
Mahesh Mehendale
Impact of Logic Module Routing Flexibility on the Routability of Antifuse-Based Channelled FPGA Architectures. VLSI Design (1994)
Mahesh Mehendale, Kaushik Roy
Estimating Area Efficiency of Antifuse Based Channelled FPGA Architectures. VLSI Design (1993)
Mahesh Mehendale
MIM: Logic Module Independent Technology Mapping for Design and Evaluation of Antifuse-based FPGAs. DAC (1993)
Mahesh Mehendale
A System for Behavior Extraction from FPGA Implementations of Synchronous Designs. VLSI Design (1992)
Mahesh Mehendale, P. Murugavel, M. Poornima
SLIM: A System for ASIC Library Management. ICCAD (1991)
Mahesh Mehendale
An approach to design flow management in CAD frameworks. EURO-DAC (1991)
Sattam Dasgupta, Mahesh Mehendale, V. R. Sudershan, Rajeev Jain, Nagaraj Subramanyam, James Hochschild
FDT-a design tool for switched capacitor filters. ICCAD (1989)