Vinod Menezes

Publication Activity (10 Years)

Years Active: 1996-2022
Publications (10 Years): 6

Top Topics

Bayesian Classifier

Power Management

Tumor Classification

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Neha Gupta, Ashish Joshi, Dinesh Kushwaha, Vinod Menezes, Rashmi Sachan, Sudeb Dasgupta, Anand Bulusu
A Multibit MAC Scheme using Switched Capacitor based 3C Multiplier for Analog Compute In-Memory Architecture. ICECS 2022 (2022)
Vipul Singhal, Rajat Chauhan, Vinod Menezes, R. R. Manikandan, Raveesh Magod, Mahesh Mehendale, Anantha P. Chandrakasan
150nA IQ, Quad Input - Quad Output, Intelligent Integrated Power Management for IoT Applications. VLSI Design (2021)
Sundeep Javvaji, Vipul Singhal, Vinod Menezes, Rajat Chauhan, Shanthi Pavan
Analysis and Design of a Multi-Step Bias-Flip Rectifier for Piezoelectric Energy Harvesting. IEEE J. Solid State Circuits 54 (9) (2019)
Kishalay Datta, Vinod Menezes, Shanthi Pavan
Analysis and Design of Cyclic Switched-Capacitor DC-DC Converters. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2019)
Sundeep Javvaji, Vipul Singhal, Vinod Menezes, Rajat Chauhan, Shanthi Pavan
Multi-Step Bias-Flip Rectification for Piezoelectric Energy Harvesting. ESSCIRC (2018)
R. R. Manikandan, Vipul Kumar Singhal, Rajat Chauhan, Vinod Menezes, Mahesh Mehendale
A 1.2 pJ/cycle KHz Timer Circuit for Heavily Duty-Cycled Systems. VLSI Design (2018)
Vipul Kumar Singhal, Vinod Menezes, Srinivasa Chakravarthy, Mahesh Mehendale
8.3 A 10.5μA/MHz at 16MHz single-cycle non-volatile memory access microcontroller with full state retention at 108nA in a 90nm process. ISSCC (2015)
Rashmi Sachan, Shahid Ali, Chandan Bist, Sunil Misra, Vinod Menezes, Sharad Gupta, Pat Bosshart
A 40nm 650Mhz 0.5fJ/Bit/Search TCAM Compiler Using Complementary Bit-cell Architecture. VLSI Design (2013)
Michael Clinton, Clive Bittlestone, G. Girishankar, Viet Le, Vinod Menezes
Design and technology interaction beyond 32nm. CICC (2011)
Karthik Rajagopal, Aatmesh, Vinod Menezes
An enhanced topology for reliability of a high performance 3.3V I/O buffer in a single-well bulk CMOS 1.8v-oxide low voltage process. ISQED (2009)
Ankur Gupta, Rajat Chauhan, Vinod Menezes, Vikas Narang, H. M. Roopashree
A Robust Level-Shifter Design for Adaptive Voltage Scaling. VLSI Design (2008)
Rachit Kumar Gupta, Vikas Narang, H. M. Roopashree, Vinod Menezes
A low-power 333Mbps mobile-double data rate output driver with adaptive feedback to minimize overshoots and undershoots. ACM Great Lakes Symposium on VLSI (2007)
Rajat Chauhan, Karthik Rajagopal, Vinod Menezes, H. M. Roopashree, Sanish Koshy Jacob
A high performance, high voltage output buffer in a low voltage CMOS process. CICC (2005)
Vinod Menezes, C. B. Keshav, Sushil Gupta, M. Roopashree, S. Krishnan, A. Amerasekera, G. Palau
Optimization of 1.8V I/O circuits for performance, reliability at the 100nm technology node. VLSI Design (2003)
Vinod Menezes, S. K. Nandy, Biswadip Mitra
Signal compression through spatial frequency-based motion estimation. Integr. 22 (1-2) (1997)
Vinod Menezes, Soumitra Kumar Nandy, Biswadip Mitra
Spatial frequency based motion estimation for image sequence compression. HiPC (1996)