Anand Bulusu

Publication Activity (10 Years)

Years Active: 2011-2024
Publications (10 Years): 45

Top Topics

Design Methodology

Lazy Evaluation

Top Venues

Publications

Aditya Sharma, Vatsal Dixit, Dinesh Kushwaha, Nitanshu Chauhan, Vishal Kumar Saxena, Sudeb Dasgupta, Anand Bulusu
Time-Domain-Based Non-volatile In-Memory Computing Architecture Using FeFETs for Binary Neural Network. ISQED (2024)
Subhradip Chakraborty, Dinesh Kushwaha, Anand Bulusu, Sudeb Dasgupta
An Area and Energy-Efficient SRAM Based Time - Domain Compute-In-Memory Architecture For BNN. AICAS (2024)
Subhradip Chakraborty, Dinesh Kushwaha, Abhishek Goel, Anmol Singla, Anand Bulusu, Sudeb Dasgupta
An Energy-Efficient Time Domain Based Compute In-Memory Architecture for Binary Neural Network. ISQED (2024)
Dinesh Kushwaha, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu
SRAM-Based Hybrid Analog Compute-In-memory Architecture to Enhance the Signal Margin. ISCAS (2024)
Dinesh Kushwaha, Rajat Kohli, Jwalant Mishra, Jainendra Singh, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu
An Energy-Efficient High Signal Margin Analog Compute-In-Memory Architecture. LASCAS (2024)
Dinesh Kushwaha, Ashish Joshi, Abhishek Goel, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu
SRAM-Based Analog Compute-In-Memory Architecture Using C-2C Ladder And Signal Margin Assisted Design Methodology. ISQED (2024)
Dinesh Kushwaha, Jaya Kumar Abotula, Rajat Kohli, Jwalant Mishra, Sudeb Dasgupta, Anand Bulusu
Multi-Bit Compute-In Memory Architecture Using a C-2C Ladder Network. IEEE Trans. Circuits Syst. II Express Briefs 71 (6) (2024)
Ravi, Lomash Chandra Acharya, Mahipal Dargupally, Neha Gupta, Neeraj Mishra, Lalit Mohan Dani, Nilotpal Sarma, Devesh Dwivedi, Sudeb Dasgupta, Anand Bulusu
ABB Assisted Area Efficient Vernier Delay Line Time-to-Digital Converter for Low Voltage Applications. APCCAS (2023)
Dinesh Kushwaha, Ashish Joshi, Neha Gupta, Aditya Sharma, Sandeep Miryala, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu
An Energy-Efficient Multi-bit Current-based Analog Compute-In-Memory Architecture and design Methodology. VLSID (2023)
Mahipal Dargupally, Lomash Chandra Acharya, Khoirom Johnson Singh, Neha Gupta, Arvind K. Sharma, Sudeb Dasgupta, Anand Bulusu
An Efficient Standard Cell Design Methodology by Exploiting Body Biasing and Poly Biasing in FDSOI for NTV Regime. APCCAS (2023)
Lomash Chandra Acharya, Arvind Kumar Sharma, Neeraj Mishra, Khoirom Johnson Singh, Mahipal Dargupally, Nayakanti Sai Shabarish, Ajoy Mandal, Venkatraman Ramakrishnan, Sudeb Dasgupta, Anand Bulusu
Aging-Aware Timing Model of CMOS Inverter: Path Level Timing Performance and Its Impact on the Logical Effort. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (8) (2023)
Khoirom Johnson Singh, Lomash Chandra Acharya, Anand Bulusu, Sudeb Dasgupta
Negative capacitance gate stack and Landau FET-based voltage amplifiers and circuits: Impact of ferroelectric thickness and domain variations. Microelectron. J. 142 (2023)
Neeraj Mishra, Anchit Proch, Lomash Chandra Acharya, Sudipto Chakraborty, Anand Bulusu
Generalized Edge Propagation and Multi-Band Frequency Switching Mechanism for MSSROs. IEEE Trans. Circuits Syst. II Express Briefs 70 (9) (2023)
Dinesh Kushwaha, Rajat Kohli, Jwalant Mishra, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu
A Fully Differential 4-Bit Analog Compute-In-Memory Architecture for Inference Application. AICAS (2023)
Lomash Chandra Acharya, Anubhav Kumar, Khoirom Johnson Singh, Neha Gupta, Nayakanti Sai Shabarish, Neeraj Mishra, Mahipal Dargupally, Arvind Kumar Sharma, Venkatraman Ramakrishnan, Ajoy Mandal, Sudeb Dasgupta, Anand Bulusu
Beyond SPICE Simulation: A Novel Variability-Aware STA Methodology for Digital Timing Closure. SMACD (2023)
Ashutosh Yadav, Anand Bulusu, Surinder Singh, Sudeb Dasgupta
Radiation Hardened CMOS Programmable Bias Generator for Space Applications at 180nm. VLSID (2023)
Abhishek Acharya, Anand Bulusu
Investigation of Body Bias Impact in Si/SiGe Heterojunction Line TFETs: A Physical Insight. ISCAS (2023)
Kartikay Mani Tripathi, Madhav Pathak, Sanjeev Manhas, Anand Bulusu
A Novel Low-Power Shift-Register Controller for Digital Low-Dropout Regulators. APCCAS (2023)
Dinesh Kushwaha, Ashish Joshi, Chaudhry Indra Kumar, Neha Gupta, Sandeep Miryala, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu
An Energy-Efficient High CSNR XNOR and Accumulation Scheme for BNN. IEEE Trans. Circuits Syst. II Express Briefs 69 (4) (2022)
Dinesh Kushwaha, Aditya Sharma, Neha Gupta, Ritik Raj, Ashish Joshi, Jwalant Mishra, Rajat Kohli, Sandeep Miryala, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu
A 65nm Compute-In-Memory 7T SRAM Macro Supporting 4-bit Multiply and Accumulate Operation by Employing Charge Sharing. ISCAS (2022)
Neeraj Mishra, Anchit Proch, Lomash Chandra Acharya, Jeffrey Prinzie, Sudipto Chakraborty, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu
Phase Noise Analysis of Separately Driven Ring Oscillators. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (11) (2022)
Nitanshu Chauhan, Chirag Garg, Kai Ni, Amit Kumar Behera, Sarita Yadav, Shashank Banchhor, Navjeet Bagga, Avirup Dasgupta, Arnab Datta, Sudeb Dasgupta, Anand Bulusu
Impact of Random Spatial Fluctuation in Non-Uniform Crystalline Phases on Multidomain MFIM Capacitor and Negative Capacitance FDSOI. IRPS (2022)
Khoirom Johnson Singh, Lomash Chandra Acharya, Anand Bulusu, Sudeb Dasgupta
Significance of Organic Ferroelectric in Harnessing Transient Negative Capacitance Effect at Low Voltage Over Oxide Ferroelectric. ISCAS (2022)
Jyoti Patel, Shashank Banchhor, Surila Guglani, Avirup Dasgupta, Sourajeet Roy, Anand Bulusu, Sudeb Dasgupta
Design optimization Using Symmetric/Asymmetric Spacer for 14 nm Multi-Fin Tri-gate Fin-FET for Mid-Band 5G Applications. VLSID (2022)
Neeraj Mishra, Lalit Mohan Dani, S. Chakraborty, Rajiv V. Joshi, Anand Bulusu
Delay Modulation in Separately Driven Delay Cells Utilized for the Generation of High-Performance Multiphase Signals Using ROs. IEEE Trans. Circuits Syst. II Express Briefs 69 (1) (2022)
Neha Gupta, Ashish Joshi, Dinesh Kushwaha, Vinod Menezes, Rashmi Sachan, Sudeb Dasgupta, Anand Bulusu
A Multibit MAC Scheme using Switched Capacitor based 3C Multiplier for Analog Compute In-Memory Architecture. ICECS 2022 (2022)
Aniket Gupta, Govind Bajpai, Navjeet Bagga, Shashank Banchhor, Sudeb Dasgupta, Anand Bulusu, Nitanshu Chauhan
Unveiling the Impact of Interface Traps Induced on Negative Capacitance Nanosheet FET: A Reliability Perspective. VDAT (2022)
Khoirom Johnson Singh, Anand Bulusu, Sudeb Dasgupta
Harnessing Maximum Negative Capacitance Signature Voltage Window in P(VDF-TrFE) Gate Stack. ISCAS (2021)
Lomash Chandra Acharya, Arvind Kumar Sharma, Venkatraman Ramakrishan, Ajoy Mandal, Sudeb Dasgupta, Anand Bulusu
Variation Aware Timing Model of CMOS Inverter for an Efficient ECSM Characterization. ISQED (2021)
Ashutosh Yadav, Anand Bulusu, Sudeb Dasgupta, Surinder Singh
Design and Fabrication of Rad-hard Low Power CMOS Temperature Sensor for Space Applications at 180nm. ICM (2021)
Lalit Mohan Dani, Neeraj Mishra, Anand Bulusu
An Efficient and Accurate Variation-Aware Design Methodology for Near-Threshold MOS-Varactor-Based VCO Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40 (10) (2021)
Sarita Yadav, Nitanshu Chauhan, Archana Pandey, Rajendra Pratap, Anand Bulusu
Behaviour of FinFET Inverter's Effective Capacitances in Low-Voltage Domain. VDAT (2021)
Neeraj Mishra, Lalit Dani, Kunal Sanvaniya, Sudeb Dasgupta, S. Chakraborty, Anand Bulusu
Design and Realization of High-Speed Low-Noise Multi-Loop Skew-Based ROs Optimized for Even/Odd Multi-Phase Signals. IEEE Trans. Circuits Syst. (11) (2020)
Chaudhry Indra Kumar, Ishant Bhatia, Arvind Kumar Sharma, Deep Sehgal, H. S. Jatana, Anand Bulusu
A Physics-Based Variability-Aware Methodology to Estimate Critical Charge for Near-Threshold Voltage Latches. IEEE Trans. Very Large Scale Integr. Syst. 27 (9) (2019)
Chaudhry Indra Kumar, Arvind Kumar Sharma, Rajendra Partap, Anand Bulusu
An energy-efficient variation aware self-correcting latch. Microelectron. J. 84 (2019)
Chaudhry Indra Kumar, Anand Bulusu
High performance energy efficient radiation hardened latch for low voltage applications. Integr. 66 (2019)
Arvind Kumar Sharma, Naushad Alam, Anand Bulusu
UTBB FD-SOI Circuit Design using Multifinger Transistors: A Circuit-Device Interaction Perspective. PRIME (2018)
Chaudhry Indra Kumar, Anand Bulusu
Design and Analysis of Energy Efficient Self Correcting Latches considering Metastability. PRIME (2018)
Archana Pandey, Pitul Garg, Shobhit Tyagi, Rajeev Ranjan, Anand Bulusu
A modified method of logical effort for FinFET circuits considering impact of fin-extension effects. ISQED (2018)
Satish Maheshwaram, Om. Prakash, Mohit Sharma, Anand Bulusu, Sanjeev Manhas
Vertical Nanowire FET Based Standard Cell Design Employing Verilog-A Compact Model for Higher Performance. VDAT (2017)
Chaudhry Indra Kumar, Arvind Kumar Sharma, Sandeep Miryala, Anand Bulusu
A novel energy-efficient self-correcting methodology employing INWE. SMACD (2016)
Archana Pandey, Harsh Kumar, Praanshu Goyal, Sudeb Dasgupta, S. K. Manhas, Anand Bulusu
FinFET Device Circuit Co-design Issues: Impact of Circuit Parameters on Delay. VLSI Design (2016)
Om. Prakash, Mohit Sharma, Anand Bulusu, A. K. Saxena, S. K. Manhas, Satish Maheshwaram
Lateral silicon nanowire based standard cell design for higher performance. APCCAS (2016)
Om. Prakash, Satish Maheshwaram, Mohit Sharma, Anand Bulusu, A. K. Saxena, S. K. Manhas
A unified Verilog-A compact model for lateral Si nanowire (NW) FET incorporating parasitics for circuit simulation. VDAT (2016)
Arvind Kumar Sharma, Neeraj Mishra, Naushad Alam, Sudeb Dasgupta, Anand Bulusu
Pre-layout estimation of performance and design of basic analog circuits in stress enabled technologies. VDAT (2015)
Parmanand Singh, Vivek Asthana, Radhakrishnan Sithanandam, Anand Bulusu, Sudeb Dasgupta
Analytical Modeling of Sub-onset Current of Tunnel Field Effect Transistor. VLSI Design (2014)
Menka Yadav, Anand Bulusu, Sudeb Dasgupta
Two dimensional analytical modeling for asymmetric 3T and 4T double gate tunnel FET in sub-threshold region: Potential and electric field. Microelectron. J. 44 (12) (2013)
Gunti Nagendra Babu, Brajesh Kumar Kaushik, Anand Bulusu, Manoj Kumar Majumder
Low Complexity Encoder for Crosstalk Reduction in RLC Modeled Interconnects. VDAT (2012)
Arnab Kumar Biswas, Anand Bulusu, Sudeb Dasgupta
A Proposed Output Buffer at 90 nm Technology with Minimum Signal Switching Noise at 83.3MHz. ISVLSI (2011)