S. K. Manhas

Publication Activity (10 Years)

Years Active: 2001-2016
Publications (10 Years): 5

Top Topics

Kolmogorov Smirnov

Top Venues

Microelectron. J.

Publications

Sarvesh Agarwal, S. K. Manhas, Sudeb Dasgupta, Neeraj Jain
Metal Carbon Nanotube Schottky Barrier Diode with Detection of Polar Non-polar Gases. VLSI Design (2016)
Archana Pandey, Harsh Kumar, Praanshu Goyal, Sudeb Dasgupta, S. K. Manhas, Anand Bulusu
FinFET Device Circuit Co-design Issues: Impact of Circuit Parameters on Delay. VLSI Design (2016)
Baljit Kaur, Arvind Kumar Sharma, Naushad Alam, S. K. Manhas, Bulusu Anand
A variation aware timing model for a 2-input NAND gate and its use in sub-65 nm CMOS standard cell characterization. Microelectron. J. 53 (2016)
Om. Prakash, Mohit Sharma, Anand Bulusu, A. K. Saxena, S. K. Manhas, Satish Maheshwaram
Lateral silicon nanowire based standard cell design for higher performance. APCCAS (2016)
Om. Prakash, Satish Maheshwaram, Mohit Sharma, Anand Bulusu, A. K. Saxena, S. K. Manhas
A unified Verilog-A compact model for lateral Si nanowire (NW) FET incorporating parasitics for circuit simulation. VDAT (2016)
Gaurav Kaushal, H. Jeong, Satish Maheshwaram, S. K. Manhas, Sudeb Dasgupta, Seong-Ook Jung
Low power SRAM design for 14 nm GAA Si-nanowire technology. Microelectron. J. 46 (12) (2015)
Ashish Joshi, S. K. Manhas, Satinder K. Sharma, Sudeb Dasgupta
An 8 bit, 100 kS/s, switch-capacitor DAC SAR ADC for RFID applications. Microelectron. J. 46 (6) (2015)
Baljit Kaur, Naushad Alam, S. K. Manhas, Bulusu Anand
Efficient ECSM Characterization Considering Voltage, Temperature, and Mechanical Stress Variability. IEEE Trans. Circuits Syst. I Regul. Pap. (12) (2014)
Baljit Kaur, Sandeep Miryala, S. K. Manhas, Bulusu Anand
An efficient method for ECSM characterization of CMOS inverter in nanometer range technologies. ISQED (2013)
Manoj Kumar Majumder, Nisarg D. Pandya, Brajesh Kumar Kaushik, S. K. Manhas
Comparison of crosstalk delay between single and bundled SWNT for global VLSI interconnects. RAIT (2012)
Manoj Kumar Majumder, Nisarg D. Pandya, Brajesh Kumar Kaushik, S. K. Manhas
Analysis of crosstalk delay and area for MWNT and bundled SWNT in global VLSI interconnects. ISQED (2012)
Baljit Kaur, Sandeep Vundavalli, S. K. Manhas, Sudeb Dasgupta, Bulusu Anand
An accurate current source model for CMOS based combinational logic cell. ISQED (2012)
Pankaj Kumar Das, Manoj Kumar Majumder, Brajesh Kumar Kaushik, S. K. Manhas
Propagation Delay Analysis for Bundled Multi-Walled CNT in Global VLSI Interconnects. SocProS (2012)
S. K. Manhas, N. Singh, G. Q. Lo
Barrier layer thickness analysis for reliable copper plug process in CMOS technology. Microelectron. Reliab. 51 (8) (2011)
Satish Maheshwaram, Gaurav Kaushal, S. K. Manhas
A high performance vertical Si nanowire CMOS for ultra high density circuits. APCCAS (2010)
Merlyne M. De Souza, S. K. Manhas, D. Chandra Sekhar, A. S. Oates, Prasad Chaparala
Influence of mobility model on extraction of stress dependent source-drain series resistance. Microelectron. Reliab. 44 (1) (2004)
S. K. Manhas, D. Chandra Sekhar, A. S. Oates, Merlyne M. De Souza
Characterisation of series resistance degradation through charge pumping technique. Microelectron. Reliab. 43 (4) (2003)
Merlyne M. De Souza, J. Wang, S. K. Manhas, E. M. Sankara Narayanan, A. S. Oates
A comparison of early stage hot carrier degradation behaviour in 5 and 3 V sub-micron low doped drain metal oxide semiconductor field effect transistors. Microelectron. Reliab. 41 (2) (2001)