Satish Maheshwaram

Publication Activity (10 Years)

Years Active: 2010-2023
Publications (10 Years): 8

Top Topics

Index Selection

Physical Design

Top Venues

Microelectron. J.

Publications

Ravi Kothapally, Vadthiya Narendar, Satish Maheshwaram
NDR free negative capacitance CGAAFET at 2nm technology node for low power and high-speed applications. Microelectron. J. 142 (2023)
Kallepelli Sagar, Satish Maheshwaram, Vadthiya Narendar
Performance analysis of geometric variations in circular double gate MOSFETs at sub-7nm technology nodes. Microelectron. J. 142 (2023)
Rudravaram Srikanth, Satish Maheshwaram
Emerging Two Dimensional Channel Materials for MOSFETs: A Review. iSES (2022)
Nikita Dindhoria, G. S. Rohit Reddy, Satish Maheshwaram
Resistive Calibrated Zero Temperature Coefficient Band Gap Reference (BGR). iSES (2022)
Neha Karna, Jagannadha Rao Arisankula, Satish Maheshwaram
Impact on the Performance of North Bridge I/O Peripheral Component Interconnect Express Block in Physical Design Flow Considering Two Different Synthesis Corners at below 10nm Technology Node. iSES (2022)
Satish Maheshwaram, Om. Prakash, Mohit Sharma, Anand Bulusu, Sanjeev Manhas
Vertical Nanowire FET Based Standard Cell Design Employing Verilog-A Compact Model for Higher Performance. VDAT (2017)
Om. Prakash, Mohit Sharma, Anand Bulusu, A. K. Saxena, S. K. Manhas, Satish Maheshwaram
Lateral silicon nanowire based standard cell design for higher performance. APCCAS (2016)
Om. Prakash, Satish Maheshwaram, Mohit Sharma, Anand Bulusu, A. K. Saxena, S. K. Manhas
A unified Verilog-A compact model for lateral Si nanowire (NW) FET incorporating parasitics for circuit simulation. VDAT (2016)
Gaurav Kaushal, H. Jeong, Satish Maheshwaram, S. K. Manhas, Sudeb Dasgupta, Seong-Ook Jung
Low power SRAM design for 14 nm GAA Si-nanowire technology. Microelectron. J. 46 (12) (2015)
Satish Maheshwaram, Gaurav Kaushal, S. K. Manhas
A high performance vertical Si nanowire CMOS for ultra high density circuits. APCCAS (2010)