• search
    search
  • reviewers
    reviewers
  • feeds
    feeds
  • assignments
    assignments
  • settings
  • logout

Vertical Nanowire FET Based Standard Cell Design Employing Verilog-A Compact Model for Higher Performance.

Satish MaheshwaramOm. PrakashMohit SharmaAnand BulusuSanjeev Manhas
Published in: VDAT (2017)
Keyphrases