A high performance vertical Si nanowire CMOS for ultra high density circuits.
Satish MaheshwaramGaurav KaushalS. K. ManhasPublished in: APCCAS (2010)
Keyphrases
- high density
- high speed
- analog vlsi
- delay insensitive
- chemical vapor deposition
- circuit design
- field effect transistors
- low density
- gate dielectrics
- low power
- metal oxide
- vlsi circuits
- low latency
- close proximity
- cmos technology
- focal plane
- plasma etching
- thin film
- high power
- high bandwidth
- data center
- power dissipation
- floating gate
- chip design
- si sio
- magnetic recording
- magnetic tape
- random access memory
- low voltage
- power consumption
- low cost
- real time
- cost effective
- analog circuits
- data model