Login / Signup

A unified Verilog-A compact model for lateral Si nanowire (NW) FET incorporating parasitics for circuit simulation.

Om. PrakashSatish MaheshwaramMohit SharmaAnand BulusuA. K. SaxenaS. K. Manhas
Published in: VDAT (2016)
Keyphrases
  • computational model
  • mathematical model
  • experimental data
  • simulation model
  • simulation software
  • high level
  • markov chain
  • theoretical analysis
  • petri net
  • formal model
  • mathematical analysis
  • simulation models