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A unified Verilog-A compact model for lateral Si nanowire (NW) FET incorporating parasitics for circuit simulation.
Om. Prakash
Satish Maheshwaram
Mohit Sharma
Anand Bulusu
A. K. Saxena
S. K. Manhas
Published in:
VDAT (2016)
Keyphrases
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computational model
mathematical model
experimental data
simulation model
simulation software
high level
markov chain
theoretical analysis
petri net
formal model
mathematical analysis
simulation models