Arvind Kumar Sharma

Publication Activity (10 Years)

Years Active: 2009-2023
Publications (10 Years): 14

Top Topics

Simulation Model

Top Venues

Microelectron. J.

Publications

Lomash Chandra Acharya, Arvind Kumar Sharma, Neeraj Mishra, Khoirom Johnson Singh, Mahipal Dargupally, Nayakanti Sai Shabarish, Ajoy Mandal, Venkatraman Ramakrishnan, Sudeb Dasgupta, Anand Bulusu
Aging-Aware Timing Model of CMOS Inverter: Path Level Timing Performance and Its Impact on the Logical Effort. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (8) (2023)
Lomash Chandra Acharya, Anubhav Kumar, Khoirom Johnson Singh, Neha Gupta, Nayakanti Sai Shabarish, Neeraj Mishra, Mahipal Dargupally, Arvind Kumar Sharma, Venkatraman Ramakrishnan, Ajoy Mandal, Sudeb Dasgupta, Anand Bulusu
Beyond SPICE Simulation: A Novel Variability-Aware STA Methodology for Digital Timing Closure. SMACD (2023)
Mohammad Haider Syed, Kamal Upreti, Mohammad Shahnawaz Nasir, Mohammad Shabbir Alam, Arvind Kumar Sharma
Addressing image and Poisson noise deconvolution problem using deep learning approaches. Comput. Intell. 39 (4) (2023)
Juzheng Liu, Shiyu Su, Meghna Madhusudan, Mohsen Hassanpourghadi, Samuel Saunders, Qiaochu Zhang, Rezwan A. Rasul, Yaguang Li, Jiang Hu, Arvind Kumar Sharma, Sachin S. Sapatnekar, Ramesh Harjani, Anthony Levi, Sandeep Gupta, Mike Shuo-Wei Chen
From Specification to Silicon: Towards Analog/Mixed-Signal Design Automation using Surrogate NN Models with Transfer Learning. ICCAD (2021)
Lomash Chandra Acharya, Arvind Kumar Sharma, Venkatraman Ramakrishan, Ajoy Mandal, Sudeb Dasgupta, Anand Bulusu
Variation Aware Timing Model of CMOS Inverter for an Efficient ECSM Characterization. ISQED (2021)
Chaudhry Indra Kumar, Ishant Bhatia, Arvind Kumar Sharma, Deep Sehgal, H. S. Jatana, Anand Bulusu
A Physics-Based Variability-Aware Methodology to Estimate Critical Charge for Near-Threshold Voltage Latches. IEEE Trans. Very Large Scale Integr. Syst. 27 (9) (2019)
Chaudhry Indra Kumar, Arvind Kumar Sharma, Rajendra Partap, Anand Bulusu
An energy-efficient variation aware self-correcting latch. Microelectron. J. 84 (2019)
Arvind Kumar Sharma, Naushad Alam, Anand Bulusu
UTBB FD-SOI Circuit Design using Multifinger Transistors: A Circuit-Device Interaction Perspective. PRIME (2018)
Sayyaparaju Sagar Varma, Arvind Kumar Sharma, Bulusu Anand
An efficient methodology to characterize the TSPC flip flop setup time for static timing analysis. SMACD (2016)
Chaudhry Indra Kumar, Arvind Kumar Sharma, Sandeep Miryala, Anand Bulusu
A novel energy-efficient self-correcting methodology employing INWE. SMACD (2016)
Baljit Kaur, Arvind Kumar Sharma, Naushad Alam, S. K. Manhas, Bulusu Anand
A variation aware timing model for a 2-input NAND gate and its use in sub-65 nm CMOS standard cell characterization. Microelectron. J. 53 (2016)
Arvind Kumar Sharma, Yogendra Sharma, Sudeb Dasgupta, Bulusu Anand
Efficient static D-latch standard cell characterization using a novel setup time model. ISQED (2015)
Yogesh Chaurasiya, Surabhi Bhargava, Arvind Kumar Sharma, Baljit Kaur, Bulusu Anand
Timing model for two stage buffer and its application in ECSM characterization. VDAT (2015)
Arvind Kumar Sharma, Neeraj Mishra, Naushad Alam, Sudeb Dasgupta, Anand Bulusu
Pre-layout estimation of performance and design of basic analog circuits in stress enabled technologies. VDAT (2015)
Bijay Kumar Dalai, N. Karnnan, Arvind Kumar Sharma, Bulusu Anand
An empirical delta delay model for highly scaled CMOS inverter considering Well Proximity Effect. VDAT (2014)
Amol Vasudeva, Arvind Kumar Sharma, Ashish Kumar
Saksham: Customizable x86 Based Multi-Core Microprocessor Simulator. CICSyN (2009)