Chaudhry Indra Kumar

Publication Activity (10 Years)

Years Active: 2011-2024
Publications (10 Years): 10

Top Topics

Energy Efficient

Thresholding Method

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Ananya Kapoor, Ayush Thapar, Chaitanya Shanker Jha, Chaudhry Indra Kumar
A High Performance and Low Power Subthreshold Voltage Level Shifter Design. VLSID (2024)
Chaudhry Indra Kumar, Abhishek Chaudhary, Shreyansh Upadhyaya
Design of high performance energy efficient CMOS voltage level shifter for mixed signal circuits applications. Integr. 95 (2024)
Raghav Shekhar, Chaudhry Indra Kumar
Design of highly reliable radiation hardened 10T SRAM cell for low voltage applications. Integr. 87 (2022)
Dinesh Kushwaha, Ashish Joshi, Chaudhry Indra Kumar, Neha Gupta, Sandeep Miryala, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu
An Energy-Efficient High CSNR XNOR and Accumulation Scheme for BNN. IEEE Trans. Circuits Syst. II Express Briefs 69 (4) (2022)
Chaudhry Indra Kumar
An Energy-Efficient Low-Area Double-Node-Upset-Hardened Latch Design. J. Circuits Syst. Comput. 31 (7) (2022)
Chaudhry Indra Kumar, Ishant Bhatia, Arvind Kumar Sharma, Deep Sehgal, H. S. Jatana, Anand Bulusu
A Physics-Based Variability-Aware Methodology to Estimate Critical Charge for Near-Threshold Voltage Latches. IEEE Trans. Very Large Scale Integr. Syst. 27 (9) (2019)
Chaudhry Indra Kumar, Arvind Kumar Sharma, Rajendra Partap, Anand Bulusu
An energy-efficient variation aware self-correcting latch. Microelectron. J. 84 (2019)
Chaudhry Indra Kumar, Anand Bulusu
High performance energy efficient radiation hardened latch for low voltage applications. Integr. 66 (2019)
Chaudhry Indra Kumar, Anand Bulusu
Design and Analysis of Energy Efficient Self Correcting Latches considering Metastability. PRIME (2018)
Chaudhry Indra Kumar, Arvind Kumar Sharma, Sandeep Miryala, Anand Bulusu
A novel energy-efficient self-correcting methodology employing INWE. SMACD (2016)
Manisha Pattanaik, Shashank Parashar, Chaudhry Indra Kumar, Akanksha Chouhan, Vikas Mahor
A Novel Low Power Noise Tolerant High Performance Dynamic Feed through Logic Design Technique. ISED (2011)
Shashank Parashar, Chaudhry Indra Kumar, Manisha Pattanaik
An Efficient Design Technique for High Performance Dynamic Feedthrough Logic with Enhanced Noise Tolerance. ISVLSI (2011)