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Dinesh Kushwaha
ORCID
Publication Activity (10 Years)
Years Active: 2016-2024
Publications (10 Years): 13
Top Topics
Level Parallelism
Design Methodology
Clock Gating
Memory Management
Top Venues
ISQED
IEEE Trans. Circuits Syst. II Express Briefs
AICAS
ISCAS
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Publications
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Aditya Sharma
,
Vatsal Dixit
,
Dinesh Kushwaha
,
Nitanshu Chauhan
,
Vishal Kumar Saxena
,
Sudeb Dasgupta
,
Anand Bulusu
Time-Domain-Based Non-volatile In-Memory Computing Architecture Using FeFETs for Binary Neural Network.
ISQED
(2024)
Subhradip Chakraborty
,
Dinesh Kushwaha
,
Anand Bulusu
,
Sudeb Dasgupta
An Area and Energy-Efficient SRAM Based Time - Domain Compute-In-Memory Architecture For BNN.
AICAS
(2024)
Subhradip Chakraborty
,
Dinesh Kushwaha
,
Abhishek Goel
,
Anmol Singla
,
Anand Bulusu
,
Sudeb Dasgupta
An Energy-Efficient Time Domain Based Compute In-Memory Architecture for Binary Neural Network.
ISQED
(2024)
Dinesh Kushwaha
,
Rajiv V. Joshi
,
Sudeb Dasgupta
,
Anand Bulusu
SRAM-Based Hybrid Analog Compute-In-memory Architecture to Enhance the Signal Margin.
ISCAS
(2024)
Dinesh Kushwaha
,
Rajat Kohli
,
Jwalant Mishra
,
Jainendra Singh
,
Rajiv V. Joshi
,
Sudeb Dasgupta
,
Anand Bulusu
An Energy-Efficient High Signal Margin Analog Compute-In-Memory Architecture.
LASCAS
(2024)
Dinesh Kushwaha
,
Ashish Joshi
,
Abhishek Goel
,
Rajiv V. Joshi
,
Sudeb Dasgupta
,
Anand Bulusu
SRAM-Based Analog Compute-In-Memory Architecture Using C-2C Ladder And Signal Margin Assisted Design Methodology.
ISQED
(2024)
Dinesh Kushwaha
,
Jaya Kumar Abotula
,
Rajat Kohli
,
Jwalant Mishra
,
Sudeb Dasgupta
,
Anand Bulusu
Multi-Bit Compute-In Memory Architecture Using a C-2C Ladder Network.
IEEE Trans. Circuits Syst. II Express Briefs
71 (6) (2024)
Dinesh Kushwaha
,
Ashish Joshi
,
Neha Gupta
,
Aditya Sharma
,
Sandeep Miryala
,
Rajiv V. Joshi
,
Sudeb Dasgupta
,
Anand Bulusu
An Energy-Efficient Multi-bit Current-based Analog Compute-In-Memory Architecture and design Methodology.
VLSID
(2023)
Dinesh Kushwaha
,
Rajat Kohli
,
Jwalant Mishra
,
Rajiv V. Joshi
,
Sudeb Dasgupta
,
Anand Bulusu
A Fully Differential 4-Bit Analog Compute-In-Memory Architecture for Inference Application.
AICAS
(2023)
Dinesh Kushwaha
,
Ashish Joshi
,
Chaudhry Indra Kumar
,
Neha Gupta
,
Sandeep Miryala
,
Rajiv V. Joshi
,
Sudeb Dasgupta
,
Anand Bulusu
An Energy-Efficient High CSNR XNOR and Accumulation Scheme for BNN.
IEEE Trans. Circuits Syst. II Express Briefs
69 (4) (2022)
Dinesh Kushwaha
,
Aditya Sharma
,
Neha Gupta
,
Ritik Raj
,
Ashish Joshi
,
Jwalant Mishra
,
Rajat Kohli
,
Sandeep Miryala
,
Rajiv V. Joshi
,
Sudeb Dasgupta
,
Anand Bulusu
A 65nm Compute-In-Memory 7T SRAM Macro Supporting 4-bit Multiply and Accumulate Operation by Employing Charge Sharing.
ISCAS
(2022)
Neha Gupta
,
Ashish Joshi
,
Dinesh Kushwaha
,
Vinod Menezes
,
Rashmi Sachan
,
Sudeb Dasgupta
,
Anand Bulusu
A Multibit MAC Scheme using Switched Capacitor based 3C Multiplier for Analog Compute In-Memory Architecture.
ICECS 2022
(2022)
Dinesh Kushwaha
,
D. K. Mishra
A 415 nW, 0.8 V, voltage reference circuit using MOSFETs in saturation and sub-threshold regions.
ICIIS
(2016)