A Novel Low Power Noise Tolerant High Performance Dynamic Feed through Logic Design Technique.
Manisha PattanaikShashank ParasharChaudhry Indra KumarAkanksha ChouhanVikas MahorPublished in: ISED (2011)
Keyphrases
- low power
- logic circuits
- low power consumption
- noise tolerant
- single chip
- power consumption
- low cost
- high speed
- vlsi architecture
- digital signal processing
- gate array
- delay insensitive
- cmos technology
- power reduction
- vlsi circuits
- instance based learning algorithms
- design methodology
- power dissipation
- mixed signal
- signal processor
- ultra low power
- active learning