Vikas Mahor

Publication Activity (10 Years)

Years Active: 2011-2019
Publications (10 Years): 7

Top Topics

Top Venues

Circuits Syst. Signal Process.

J. Low Power Electron.

Publications

Vikas Mahor, Srishti Agrawal, Rekha Gupta
Image Filtering with Iterative Wavelet Transform Based Compression. ICACDS (2) (2019)
Vikas Mahor, Manisha Pattanaik
A State-of-the-Art Current Mirror-Based Reliable Wide Fan-in FinFET Domino OR Gate Design. Circuits Syst. Signal Process. 37 (2) (2018)
Shubhranil Kundu, Vikas Mahor, Rekha Gupta
A Highly Accurate Fire Detection Method Using Discriminate Method. ICACCI (2018)
Vikas Mahor, Manisha Pattanaik
An Aging-Aware Reliable FinFET-Based Low-Power 32-Word \(\times \) 32-bit Register File. Circuits Syst. Signal Process. 36 (12) (2017)
Akanksha Bhadoria, Mukesh Chaturvedi, Vikas Mahor, Manisha Pattanaik
Low Stand-By Power and Process Variation Tolerant FinFET Based SRAM Cell. iNIS (2016)
Mukesh Chaturvedi, Akanksha Bhadoria, Vikas Mahor, Manisha Pattanaik
FinFET-Based Low Power Address Decoder under Process Variation. iNIS (2016)
Vivek Kumar, Vikas Mahor, Manisha Pattanaik
Novel Ultra Low Leakage FinFET Based SRAM Cell. iNIS (2016)
Vikas Mahor, Manisha Pattanaik
Low Leakage and Highly Noise Immune FinFET-Based Wide Fan-In Dynamic Logic Design. J. Circuits Syst. Comput. 24 (5) (2015)
Vikas Mahor, Manisha Pattanaik
Novel NBTI Aware Approach for Low Power FinFET Based Wide Fan-In Domino Logic. J. Low Power Electron. 11 (2) (2015)
Vikas Mahor, Akanksha Chouhan, Manisha Pattanaik
A Process Variation Tolerant Low Contention Keeper Design for Wide Fan-In Dynamic OR Gate. ISED (2012)
Manisha Pattanaik, Shashank Parashar, Chaudhry Indra Kumar, Akanksha Chouhan, Vikas Mahor
A Novel Low Power Noise Tolerant High Performance Dynamic Feed through Logic Design Technique. ISED (2011)