Manisha Pattanaik

Publication Activity (10 Years)

Years Active: 2003-2024
Publications (10 Years): 32

Top Topics

Energy Efficient

Gaussian Mixture

Edge Preservation

Top Venues

Microelectron. J.

J. Circuits Syst. Comput.

Publications

Rachana Ahirwar, Manisha Pattanaik, Pankaj Srivastava
Radiation Hardened by Design-based Voltage Controlled Oscillator for Low Power Phase Locked Loop Application. J. Electron. Test. 40 (2) (2024)
Richa Sharma, G. K. Sharma, Manisha Pattanaik
Adversarial Label Flipping Attack on Supervised Machine Learning-Based HT Detection Systems. ISCAS (2024)
Anil Kumar Rajput, Alok Kumar Tiwari, Manisha Pattanaik
An Energy-Efficient Hybrid SRAM-Based In-Memory Computing Macro for Artificial Intelligence Edge Devices. Circuits Syst. Signal Process. 42 (6) (2023)
Anil Kumar Rajput, Manisha Pattanaik
Local bit line 8T SRAM based in-memory computing architecture for energy-efficient linear error correction codec implementation. Microelectron. J. 137 (2023)
Richa Sharma, G. K. Sharma, Manisha Pattanaik
Novel Label Flipping Dataset Poisoning Attack Against ML-Based HT Detection Systems. APCCAS (2023)
Richa Sharma, G. K. Sharma, Manisha Pattanaik, V. S. S. Prashant
Structural and SCOAP Features Based Approach for Hardware Trojan Detection Using SHAP and Light Gradient Boosting Model. J. Electron. Test. 39 (4) (2023)
Noopur Srivastava, Anil Kumar Rajput, Manisha Pattanaik, Gaurav Kaushal
An Energy-Efficient and Robust 10T SRAM Based in-Memory Computing Architecture. VLSID (2023)
Neelam Arya, Teena Soni, Manisha Pattanaik, G. K. Sharma
Energy efficient logarithmic-based approximate divider for ASIC and FPGA-based implementations. Microprocess. Microsystems 90 (2022)
Abhishek Gupta, Somesh Kumar, Manisha Pattanaik
Coverage hole detection using social spider optimized Gaussian Mixture Model. J. King Saud Univ. Comput. Inf. Sci. 34 (Issue 10, Part B) (2022)
Anil Kumar Rajput, Manisha Pattanaik, Gaurav Kaushal
Local bit-line shared pass-gate 8T SRAM based energy efficient and reliable In-Memory Computing architecture. Microelectron. J. 129 (2022)
Richa Sharma, G. K. Sharma, Manisha Pattanaik
A CatBoost Based Approach to Detect Label Flipping Poisoning Attack in Hardware Trojan Detection Systems. J. Electron. Test. 38 (6) (2022)
Richa Sharma, G. K. Sharma, Manisha Pattanaik
A Few Shot Learning based Approach for Hardware Trojan Detection using Deep Siamese CNN. VLSI Design (2021)
Richa Sharma, Vijaypal Singh Rathor, G. K. Sharma, Manisha Pattanaik
A new hardware Trojan detection technique using deep convolutional neural network. Integr. 79 (2021)
Neelam Arya, Teena Soni, Manisha Pattanaik, G. K. Sharma
READ: A fixed restoring array based accuracy-configurable approximate divider for energy efficiency. Integr. 76 (2021)
Neelam Arya, Manisha Pattanaik, G. K. Sharma
Energy-Efficient Logarithmic Square Rooter for Error-Resilient Applications. IEEE Trans. Very Large Scale Integr. Syst. 29 (11) (2021)
Amit Kumar, Manisha Pattanaik, Pankaj Srivastava, Kamal Kishor Jha
Reduction of Drain Induced Barrier Lowering in DM-HD-NA GAAFET for RF Applications. IET Circuits Devices Syst. 14 (3) (2020)
Neelam Arya, Teena Soni, Manisha Pattanaik, G. K. Sharma
Bit significance based reconfigurable approximate restoring dividers and square rooters. Microelectron. J. 104 (2020)
Richa Sharma, Nitya Kritin Valivati, G. K. Sharma, Manisha Pattanaik
A New Hardware Trojan Detection Technique using Class Weighted XGBoost Classifier. VDAT (2020)
Neelam Arya, Teena Soni, Manisha Pattanaik, G. K. Sharma
Area and Energy Efficient Approximate Square Rooters for Error Resilient Applications. VLSI Design (2020)
Anil Kumar Rajput, Manisha Pattanaik
Energy Efficient 9T SRAM With R/W Margin Enhanced for beyond Von-Neumann Computation. VDAT (2020)
Vaishnav Chandak, Priyansh Saxena, Manisha Pattanaik, Gaurav Kaushal
Semantic Image Completion and Enhancement using Deep Learning. ICCCNT (2019)
Neelam Arya, Anil Kumar Rajput, Manisha Pattanaik, G. K. Sharma
Quality Driven Energy Aware Approximated Core Transform Architecture for HEVC Standard. VDAT (2019)
Vaishnav Chandak, Priyansh Saxena, Manisha Pattanaik, Gaurav Kaushal
Semantic Image Completion and Enhancement using Deep Learning. CoRR (2019)
Vikas Mahor, Manisha Pattanaik
A State-of-the-Art Current Mirror-Based Reliable Wide Fan-in FinFET Domino OR Gate Design. Circuits Syst. Signal Process. 37 (2) (2018)
Pratiksha Shukla, Vinay Gupta, Manisha Pattanaik
Low Leakage Read Write Enhanced 9T SRAM Cell. VDAT (2018)
Vinay Gupta, Pratiksha Shukla, Manisha Pattanaik
Low Leakage Noise Tolerant 10T SRAM Cell. VDAT (2018)
Vikas Mahor, Manisha Pattanaik
An Aging-Aware Reliable FinFET-Based Low-Power 32-Word \(\times \) 32-bit Register File. Circuits Syst. Signal Process. 36 (12) (2017)
Amit Singh Rajput, Manisha Pattanaik, R. K. Tiwari
Design and Analysis of Schmitt Trigger Based 10T SRAM in 32 nm Technology. iNIS (2017)
Akanksha Bhadoria, Mukesh Chaturvedi, Vikas Mahor, Manisha Pattanaik
Low Stand-By Power and Process Variation Tolerant FinFET Based SRAM Cell. iNIS (2016)
Mukesh Chaturvedi, Akanksha Bhadoria, Vikas Mahor, Manisha Pattanaik
FinFET-Based Low Power Address Decoder under Process Variation. iNIS (2016)
Vijay Kumar Sharma, Manisha Pattanaik
Design of Low Leakage Variability Aware ONOFIC CMOS Standard Cell Library. J. Circuits Syst. Comput. 25 (11) (2016)
Vivek Kumar, Vikas Mahor, Manisha Pattanaik
Novel Ultra Low Leakage FinFET Based SRAM Cell. iNIS (2016)
Vikas Mahor, Manisha Pattanaik
Low Leakage and Highly Noise Immune FinFET-Based Wide Fan-In Dynamic Logic Design. J. Circuits Syst. Comput. 24 (5) (2015)
Rohit Kumar, Manisha Pattanaik
A novel dual multiplier floating point multiply accumulate architecture. VDAT (2015)
Vikas Mahor, Manisha Pattanaik
Novel NBTI Aware Approach for Low Power FinFET Based Wide Fan-In Domino Logic. J. Low Power Electron. 11 (2) (2015)
Nandakishor Yadav, Shikha Jain, Manisha Pattanaik, G. K. Sharma
A novel stability and process sensitivity driven model for optimal sized FinFET based SRAM. Microelectron. Reliab. 55 (8) (2015)
Gagan Deep Verma, Manisha Pattanaik
Performance study of side block oxide band gap engineered SONOS: A device simulation approach. VDAT (2015)
Nandakishor Yadav, Manisha Pattanaik, G. K. Sharma
New Topology Approach for Future Process, Voltage and Temperature Aware SRAM Using Independently Controlled Double-Gate FinFET. J. Low Power Electron. 11 (1) (2015)
Abhishek Mishra, Kamal Kishor Jha, Manisha Pattanaik
Parameter variation aware hybrid TFET-CMOS based power gating technique with a temperature variation tolerant sleep mode. Microelectron. J. 45 (11) (2014)
Shipra Bassi, Manisha Pattanaik
TID effects on retention of 0.13 μm SONOS memory cell: A device simulation approach. VDAT (2014)
Vijay Kumar Sharma, Manisha Pattanaik
Techniques for Low Leakage nanoscale VLSI Circuits: a Comparative Study. J. Circuits Syst. Comput. 23 (5) (2014)
Vijay Kumar Sharma, Sumit Patel, Manisha Pattanaik
High Performance Process Variations Aware Technique for Sub-threshold 8T-SRAM Cell. Wirel. Pers. Commun. 78 (1) (2014)
Nafis Uddin Khan, K. V. Arya, Manisha Pattanaik
Edge preservation of impulse noise filtered images by improved anisotropic diffusion. Multim. Tools Appl. 73 (1) (2014)
Ekta Prajapati, Nandakishor Yadav, Manisha Pattanaik, G. K. Sharma
Operation-aware assist circuit design for improved write performance of FinFET based SRAM. VDAT (2014)
Vijay Kumar Sharma, Manisha Pattanaik, Balwinder Raj
PVT variations aware low leakage INDEP approach for nanoscale CMOS circuits. Microelectron. Reliab. 54 (1) (2014)
Vijay Kumar Sharma, Manisha Pattanaik
Process, Voltage and Temperature Variations Aware Low Leakage Approach for Nanoscale CMOS Circuits. J. Low Power Electron. 10 (1) (2014)
Nandakishor Yadav, Shikha Jain, Manisha Pattanaik, G. K. Sharma
NBTI aware IG-FinFET based SRAM design using adaptable trip-point sensing technique. NANOARCH (2014)
Nafis Uddin Khan, K. V. Arya, Manisha Pattanaik
Histogram statistics based variance controlled adaptive threshold in anisotropic diffusion for low contrast image enhancement. Signal Process. 93 (6) (2013)
Nandakishor Yadav, Sunil Dutt, Manisha Pattanaik, G. K. Sharma
Double-gate FinFET process variation aware 10T SRAM cell topology design and analysis. ECCTD (2013)
Vikas Mahor, Akanksha Chouhan, Manisha Pattanaik
A Process Variation Tolerant Low Contention Keeper Design for Wide Fan-In Dynamic OR Gate. ISED (2012)
Santhosh Keshavarapu, Saumya Jain, Manisha Pattanaik
A New Assist Technique to Enhance the Read and Write Margins of Low Voltage SRAM Cell. ISED (2012)
Shashikant Sharma, Manisha Pattanaik, Balwinder Raj
Signal Stepping Based Multimode Multi-threshold CMOS Technique for Ground Bounce Noise Reduction in Static CMOS Adders. ISED (2012)
Nafis Uddin Khan, K. V. Arya, Manisha Pattanaik
Fuzzy based diffusion coefficient function in anisotropic diffusion for impulse noise removal. ICVGIP (2012)
Manisha Pattanaik, Shashank Parashar, Chaudhry Indra Kumar, Akanksha Chouhan, Vikas Mahor
A Novel Low Power Noise Tolerant High Performance Dynamic Feed through Logic Design Technique. ISED (2011)
Shilpi Birla, Rakesh Kumar Singh, Manisha Pattanaik
Stability and Leakage Analysis of a Novel PP Based 9T SRAM Cell Using N Curve at Deep Submicron Technology for Multimedia Applications. Circuits Syst. 2 (4) (2011)
Shashank Parashar, Chaudhry Indra Kumar, Manisha Pattanaik
An Efficient Design Technique for High Performance Dynamic Feedthrough Logic with Enhanced Noise Tolerance. ISVLSI (2011)
Nafis Uddin Khan, K. V. Arya, Manisha Pattanaik
A New Adaptive Thresholding in SVD for Efficient Image De-noising. SocProS (2) (2011)
Shilpi Birla, Neeraj Kumar Shukla, Kapil Rathi, Rakesh Kumar Singh, Manisha Pattanaik
Analysis of 8T SRAM Cell at Various Process Corners at 65 nm Process Technology. Circuits Syst. 2 (4) (2011)
Subhra Dhar, Manisha Pattanaik, Poolla Rajaram
Advancement in Nanoscale CMOS Device Design En Route to Ultra-Low-Power Applications. VLSI Design 2011 (2011)
Deepak Kumar, Pankaj Kumar, Manisha Pattanaik
Performance analysis of dynamic threshold MOS (DTMOS) based 4-input multiplexer switch for low power and high speed FPGA design. SBCCI (2010)
Nafis Uddin Khan, K. V. Arya, Manisha Pattanaik
An efficient image noise removal and enhancement method. SMC (2010)
Nishant Khanwalkar, Shashikala Tapaswi, Manisha Pattanaik
An Efficient Compressed Domain Spatial Transcoding Scheme for Adaptive Video Content Delivery. PCM (2) (2010)
Deepak Kumar, Pankaj Kumar, Manisha Pattanaik
Performance Analysis of 90nm Look Up Table (LUT) for Low Power Application. DSD (2010)
Manisha Pattanaik, Swapna Banerjee
A New Approach to Analyze a Sub-micron CMOS Inverter. VLSI Design (2003)