Local bit line 8T SRAM based in-memory computing architecture for energy-efficient linear error correction codec implementation.
Anil Kumar RajputManisha PattanaikPublished in: Microelectron. J. (2023)
Keyphrases
- error correction
- energy efficient
- random access memory
- design considerations
- wireless sensor networks
- energy consumption
- data transmission
- magnetic tape
- multi core architecture
- memory management
- sensor networks
- memory access
- analog to digital converter
- energy efficiency
- channel coding
- error detection
- power consumption
- error correcting
- single instruction multiple data
- base station
- hardware architecture
- low complexity
- sensor nodes
- instruction set
- high speed
- low power
- communication networks
- wireless networks
- response time