Swapna Banerjee

Publication Activity (10 Years)

Years Active: 1971-2021
Publications (10 Years): 19

Top Topics

Elimination Algorithm

Floating Point Arithmetic

Vlsi Architecture

Thermal Imaging

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Pulak Mondal, Swapna Banerjee
FPGA-accelerated adaptive projection-based image registration. J. Real Time Image Process. 18 (1) (2021)
Biswabandhu Jana, Avishek Sinha Roy, Goutam Saha, Swapna Banerjee
A Low-Error, Memory-Based Fast Binary Logarithmic Converter. IEEE Trans. Circuits Syst. II Express Briefs (10) (2020)
Pallab Kumar Nath, Swapna Banerjee
A high throughput pass parallel block decoder architecture for JPEG 2000 that prevents stalling in the decoding process. Integr. 71 (2020)
Arindrajit Ghosh, Uddalak Bhattacharya, Manish Kumar, Swapna Banerjee
8T 1R1W register file in 14 nm FinFET technology. Integr. 70 (2020)
Biswabandhu Jana, Rakesh Biswas, Pallab Kumar Nath, Goutam Saha, Swapna Banerjee
Smartphone-Based Point-of-Care System Using Continuous-Wave Portable Doppler. IEEE Trans. Instrum. Meas. 69 (10) (2020)
Pulak Mondal, Swapna Banerjee
A Reconfigurable Memory-Based Fast VLSI Architecture for Computation of the Histogram. IEEE Trans. Consumer Electron. 65 (2) (2019)
Mayur Agarwal, Arijit De, Swapna Banerjee
An IEEE Single Precision Floating Point Arithmetic-Based Apodization Architecture for Portable Ultrasound Imaging System. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2019)
Biswabandhu Jana, Kamal Oswal, Sankar Mitra, Goutam Saha, Swapna Banerjee
Detection of peripheral arterial disease using Doppler spectrogram based expert system for Point-of-Care applications. Biomed. Signal Process. Control. 54 (2019)
Rakesh Biswas, Siddarth Reddy Malreddy, Swapna Banerjee
A High-Precision Low-Area Unified Architecture for Lossy and Lossless 3D Multi-Level Discrete Wavelet Transform. IEEE Trans. Circuits Syst. Video Technol. 28 (9) (2018)
Praful P. Pai, Pradyut Kumar Sanki, Sudeep K. Sahoo, Arijit De, Sourangshu Bhattacharya, Swapna Banerjee
Cloud Computing-Based Non-Invasive Glucose Monitoring for Diabetic Care. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2018)
Indranil Hatai, Indrajit Chakrabarti, Swapna Banerjee
A Computationally Efficient Reconfigurable Constant Multiplication Architecture Based on CSD Decoded Vertical-Horizontal Common Sub-Expression Elimination Algorithm. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2018)
Praful P. Pai, Arijit De, Swapna Banerjee
Accuracy Enhancement for Noninvasive Glucose Estimation Using Dual-Wavelength Photoacoustic Measurements and Kernel-Based Calibration. IEEE Trans. Instrum. Meas. 67 (1) (2018)
Arindrajit Ghosh, Uddalak Bhattacharya, Swapna Banerjee
Contention free delayed keeper for high density large signal sensing memory compiler. Integr. 62 (2018)
Ashutosh Mishra, Sudipta Mahapatra, Swapna Banerjee
A Low Complexity VLSI Architecture for Multi-Focus Image Fusion in DCT Domain. CoRR (2016)
Mrityunjoy Chakraborty, Sudipta Mukhopadhyay, A. Dasgupta, Swapna Banerjee, S. Patsa, J. G. Ray, K. Chaudhuri
A new paradigm of oral cancer detection using digital infrared thermal imaging. Medical Imaging: Computer-Aided Diagnosis (2016)
Pulak Mondal, Pradyut Kumar Biswal, Swapna Banerjee
FPGA based accelerated 3D affine transform for real-time image processing applications. Comput. Electr. Eng. 49 (2016)
Mayur Agarwal, Arijit De, Swapna Banerjee
Architecture of a real-time delay calculator for digital beamforming in ultrasound system. IET Circuits Devices Syst. 10 (4) (2016)
Biswabandhu Jana, Swapna Banerjee
Implementation of Smartphone Based Blood Flow Diagnoses from Doppler Spectrogram. CBMS (2016)
Pallab Kumar Nath, Swapna Banerjee
A high speed, memory efficient line based VLSI architecture for the dual mode inverse discrete wavelet transform of JPEG2000 decoder. Microprocess. Microsystems 40 (2016)
Indranil Hatai, Indrajit Chakrabarti, Swapna Banerjee
An Efficient VLSI Architecture of a Reconfigurable Pulse-Shaping FIR Interpolation. IEEE Trans. Very Large Scale Integr. Syst. 23 (6) (2015)
Satyabrata Sarangi, Swapna Banerjee
Efficient Hardware Implementation of Encoder and Decoder for Golay Code. IEEE Trans. Very Large Scale Integr. Syst. 23 (9) (2015)
Rakesh Biswas, Kishor Sarawadekar, Srinivas Varna, Swapna Banerjee
An FPGA-based architecture of DSC-SRI units specially for motion blind ultrasound systems. J. Real Time Image Process. 10 (3) (2015)
Praful P. Pai, Pradyut Kumar Sanki, Swapna Banerjee
A photoacoustics based continuous non-invasive blood glucose monitoring system. MeMeA (2015)
Indranil Hatai, Indrajit Chakrabarti, Swapna Banerjee
An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis. IEEE Trans. Circuits Syst. I Regul. Pap. (4) (2015)
Santanu Sarkar, Swapna Banerjee
A 10-Bit 500 MSPS Segmented DAC with Optimized Current Sources to Avoid Mismatch Effect. ISVLSI (2015)
Ashutosh Mishra, Pulak Mondal, Swapna Banerjee
VLSI-Assisted Nonrigid Registration Using Modified Demons Algorithm. IEEE Trans. Very Large Scale Integr. Syst. 23 (12) (2015)
Praful P. Pai, Pradyut Kumar Sanki, Arijit De, Swapna Banerjee
NIR photoacoustic spectroscopy for non-invasive glucose measurement. EMBC (2015)
Santanu Sarkar, Swapna Banerjee
An 8-bit low power DAC with re-used distributed binary cells architecture for reconfigurable transmitters. Microelectron. J. 45 (6) (2014)
Ashutosh Mishra, Pulak Mondal, Swapna Banerjee
2D/3D Non-rigid Image Registration by an Efficient Demons Approach. CBMS (2014)
Satyabrata Sarangi, Praful P. Pai, Pradyut Kumar Sanki, Swapna Banerjee
Comparative Analysis of Golay Code Based Excitation and Coherent Averaging for Non-invasive Glucose Monitoring System. CBMS (2014)
Pradyut Kumar Biswal, Pulak Mondal, Swapna Banerjee
Parallel architecture for accelerating affine transform in high-speed imaging systems. J. Real Time Image Process. 8 (1) (2013)
Indranil Hatai, Indrajit Chakrabarti, Swapna Banerjee
Reconfigurable Architecture of a RRC Fir Interpolator for Multi-standard Digital Up Converter. IPDPS Workshops (2013)
Sounak Roy, Hiranmoy Basak, Swapna Banerjee
Foreground calibration technique of a pipeline ADC using capacitor ratio of Multiplying Digital-to-Analog Converter (MDAC). Microelectron. J. 44 (12) (2013)
Sounak Roy, Bibhudatta Sahoo, Swapna Banerjee
Radix based digital calibration technique for pipelined ADC using Nyquist sampling of sinusoid. ISCAS (2012)
Pulak Mondal, Swapna Banerjee
Motion estimation in medical video sequences using affine transform. CBMS (2012)
Kishor Sarawadekar, Harihar Bharat Indana, Deep Bera, Swapna Banerjee
VLSI-DSP based real time solution of DSC-SRI for an ultrasound system. Microprocess. Microsystems 36 (1) (2012)
Ashutosh Mishra, Pulak Mondal, Swapna Banerjee
Modified Demons deformation algorithm for non-rigid image registration. IHCI (2012)
Kishor Sarawadekar, Swapna Banerjee
VLSI design of memory-efficient, high-speed baseline MQ coder for JPEG 2000. Integr. 45 (1) (2012)
Kishor Sarawadekar, Swapna Banerjee
An Efficient Pass-Parallel Architecture for Embedded Block Coder in JPEG 2000. IEEE Trans. Circuits Syst. Video Technol. 21 (6) (2011)
Vijaya Bhadauria, Krishna Kant, Swapna Banerjee
A tunable transconductor with high linearity. APCCAS (2010)
Kaushik Bhattacharyya, Rakesh Biswas, Anindya Sundar Dhar, Swapna Banerjee
Architectural design and FPGA implementation of radix-4 CORDIC processor. Microprocess. Microsystems 34 (2-4) (2010)
Anirban Das, Anindya Hazra, Swapna Banerjee
An Efficient Architecture for 3-D Discrete Wavelet Transform. IEEE Trans. Circuits Syst. Video Technol. 20 (2) (2010)
Kishor Sarawadekar, Swapna Banerjee
A high speed bit plane coder for JPEG 2000 and it's FPGA implementation. EUSIPCO (2009)
Kishor Sarawadekar, Swapna Banerjee
Efficient VLSI architecture for bit plane encoder of JPEG 2000. ICIP (2009)
Deep Bera, Leeladhar Agarwal, Swapna Banerjee
Multirate scan conversion of ultrasound images using warped distance based adaptive bilinear interpolation. CBMS (2009)
Santanu Sarkar, Swapna Banerjee
An 8-bit 1.8 V 500 MSPS CMOS Segmented Current Steering DAC. ISVLSI (2009)
Santanu Sarkar, Ravi Sankar Prasad, Sanjoy Kumar Dey, Vinay Belde, Swapna Banerjee
An 8-bit 1.8 V 500 MS/s CMOS DAC with a novel four-stage current steering architecture. ISCAS (2008)
Sounak Roy, Swapna Banerjee
A 9 bit 400 MHz CMOS Double-Sampled Sample-and-Hold Amplifier. VLSI Design (2008)
Santanu Sarkar, Arindrajit Ghosh, Swapna Banerjee
A Fully Differential 11mW 10-bit 200MS/s Sample and Hold in 0.25µm BiCMOS Technology. APCCAS (2006)
J. Bhattacharyya, P. Mandal, R. Banerjee, Swapna Banerjee
Real Time Dynamic Receive Apodization for an Ultrasound Imaging System. VLSI Design (2006)
Debashis Dutta, Ritesh Ujjwal, Swapna Banerjee
Design of Low-Voltage Low-Power Continuous-Time Filter for Hearing Aid Application Using CMOS Current Conveyor Based Translinear Loop. VLSI Design (2006)
Sanjoy Kumar Dey, Swapna Banerjee
An 8-Bit, 3.8GHz Dynamic BiCMOS Comparator for High-Performance ADC. VLSI Design (2006)
Abhijeet Jadhav, Swapna Banerjee, P. K. Dutta, Ranjan Rashmi Paul, Mousumi Pal, P. Banerjee, K. Chaudhuri, J. Chatterjee
Quantitative Analysis of Histopathological Features of Precancerous Lesion and Condition Using Image Processing Technique. CBMS (2006)
Bodhisatwa Mazumdar, Aman Mediratta, Joydeep Bhattacharyya, Swapna Banerjee
A Real Time Speckle Noise Cleaning Filter for Ultrasound Images. CBMS (2006)
Debashis Dutta, Ritesh Ujjwal, Swapna Banerjee, Wouter A. Serdijn
Design of static and dynamic translinear circuits based on CMOS CCII translinear loops. ICECS (2005)
Debashis Dutta, Wouter A. Serdijn, Swapna Banerjee, Sriram Gupta
A New CMOS Current Conveyors Based Translinear Loop for Log-Domain Circuit Design. VLSI Design (2005)
Koushik Maharatna, Swapna Banerjee, Eckhard Grass, Milos Krstic, Alfonso Troya
Modified virtually scaling-free adaptive CORDIC rotator algorithm and architecture. IEEE Trans. Circuits Syst. Video Technol. 15 (11) (2005)
Samiran Halder, Arindrajit Ghosh, Ravi Sankar Prasad, Anirban Chatterjee, Swapna Banerjee
A 160MSPS 8-Bit Pipeline Based ADC. VLSI Design (2005)
Samiran Halder, Swapna Banerjee, Arindrajit Ghosh, Ravi Sankar Prasad, Anirban Chatterjee, Sanjoy Kumar Dey
Segmented Current Steering CMOS DAC. VLSI Design (2005)
Bipul Das, Swapna Banerjee
Homogeneity Induced Inertial Snake with Application to Medical Image Segmentation. CBMS (2004)
Abhishek Mitra, Swapna Banerjee
A New Interpolation Free Method for X-ray CT Image Reconstruction. CBMS (2004)
Koushik Maharatna, Alfonso Troya, Swapna Banerjee, Eckhard Grass, Milos Krstic
A 16-bit CORDIC rotator for high-speed wireless LAN. PIMRC (2004)
Anindya Hazra, J. Bhattacharyya, Swapna Banerjee
Real Time Noise Cleaning of Ultrasound Images. CBMS (2004)
Abhishek Mitra, Swapna Banerjee
A regular algorithm for real time Radon & inverse Radon transform [image processing applications]. ICASSP (5) (2004)
Bipul Das, Swapna Banerjee
A Memory Efficient 3-D DWT Architecture. VLSI Design (2003)
Bipul Das, Swapna Banerjee
A low complexity architecture for complex discrete wavelet transform. ICASSP (2) (2003)
Bipul Das, Swapna Banerjee
A Novel Ram Architecture For Bit-Plane Based Coding. DCC (2003)
Manisha Pattanaik, Swapna Banerjee
A New Approach to Analyze a Sub-micron CMOS Inverter. VLSI Design (2003)
Bipul Das, Swapna Banerjee
A Wavelet Based Low Complexity Embedded Block Coding Algorithm. DCC (2002)
B. Das, Swapna Banerjee
VLSI architecture for a new real-time 3D wavelet transform. ICASSP (2002)
Debashis Dutta, Qadeer Ahmad Khan, Swapna Banerjee
Design of continuous-time filter for hearing aid application using current conveyors. ICECS (2002)
Koushik Maharatna, A. S. Dhar, Swapna Banerjee
A VLSI array architecture for realization of DFT, DHT, DCT and DST. Signal Process. 81 (9) (2001)
Ayan Banerjee, Anindya Sundar Dhar, Swapna Banerjee
FPGA realization of a CORDIC based FFT processor for biomedical signal processing. Microprocess. Microsystems 25 (3) (2001)
Koushik Maharatna, Swapna Banerjee
A VLSI array architecture for Hough transform. Pattern Recognit. 34 (7) (2001)
Bipul Das, Swapna Banerjee
A CORDIC based array architecture for complex discrete wavelet transform. ACM Great Lakes Symposium on VLSI (2001)
Bipul Das, S. K. Mitra, Swapna Banerjee
Knowledge Base System for Diagnostic Assessment of Doppler Spectogram. MICAI (2000)
Bipul Das, Swapna Banerjee
Knowledge-based Doppler blood-velocimeter system. KES (3) (1998)
G. Hari Rama Krishna, Amit K. Aditya, Nirmal B. Chakrabarti, Swapna Banerjee
Finite element analysis of SiGe heterojunction devices. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14 (7) (1995)
G. Hari Rama Krishna, Amit K. Aditya, Nirmal B. Chakrabarti, Swapna Banerjee
Analysis of temperature dependence of Si-Ge HBT. VLSI Design (1995)
G. Hari Rama Krishna, Nirmal B. Chakrabarti, Swapna Banerjee
Finite Element Analysis of SIGe npn HBT. VLSI Design (1994)
S. K. Mitra, Swapna Banerjee
On the Probability Distribution of Round-off Errors Propagated in Tabular Differences. Aust. Comput. J. 3 (2) (1971)