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An 8-bit 1.8 V 500 MS/s CMOS DAC with a novel four-stage current steering architecture.
Santanu Sarkar
Ravi Sankar Prasad
Sanjoy Kumar Dey
Vinay Belde
Swapna Banerjee
Published in:
ISCAS (2008)
Keyphrases
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analog to digital converter
low cost
analog vlsi
data sets
low voltage
management system
real time
design considerations
case study
control system
high speed
operating system
power consumption
low power
hardware implementation
data flow
circuit design
random access memory
learning algorithm