Santanu Sarkar

Publication Activity (10 Years)

Years Active: 2006-2022
Publications (10 Years): 1

Top Topics

Digital Elevation

Dynamic Reconfiguration

Top Venues

Microelectron. J.

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Smrutilekha Samanta, Santanu Sarkar
A Pairwise Swap Enabled Randomized DEM Addressing Intersegment Mismatch for Current Steering Digital-to-Analog Converters. IEEE Trans. Very Large Scale Integr. Syst. 30 (9) (2022)
Santanu Sarkar, Swapna Banerjee
A 10-Bit 500 MSPS Segmented DAC with Optimized Current Sources to Avoid Mismatch Effect. ISVLSI (2015)
Santanu Sarkar, Swapna Banerjee
An 8-bit low power DAC with re-used distributed binary cells architecture for reconfigurable transmitters. Microelectron. J. 45 (6) (2014)
Santanu Sarkar, Swapna Banerjee
An 8-bit 1.8 V 500 MSPS CMOS Segmented Current Steering DAC. ISVLSI (2009)
Santanu Sarkar, Ravi Sankar Prasad, Sanjoy Kumar Dey, Vinay Belde, Swapna Banerjee
An 8-bit 1.8 V 500 MS/s CMOS DAC with a novel four-stage current steering architecture. ISCAS (2008)
Santanu Sarkar, Arindrajit Ghosh, Swapna Banerjee
A Fully Differential 11mW 10-bit 200MS/s Sample and Hold in 0.25µm BiCMOS Technology. APCCAS (2006)