Smrutilekha Samanta

Publication Activity (10 Years)

Years Active: 2017-2024
Publications (10 Years): 5

Top Topics

Error Compensation

Mathematical Morphology

Figure Of Merit

Top Venues

Int. J. Circuit Theory Appl.

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Smrutilekha Samanta, Santanu Sarkar
Mismatch error compensation of hybrid CS-DAC to achieve high figure of merit utilizing on-chip self-healing assisted swap-enabled randomization technique. Int. J. Circuit Theory Appl. 52 (5) (2024)
Smrutilekha Samanta, Santanu Sarkar
A Pairwise Swap Enabled Randomized DEM Addressing Intersegment Mismatch for Current Steering Digital-to-Analog Converters. IEEE Trans. Very Large Scale Integr. Syst. 30 (9) (2022)
Smrutilekha Samanta, Santanu Sarkar
A 1.8V 8-Bit 500 MSPS Segmented Current Steering DAC with >66 dB SFDR. ISVLSI (2020)
Smrutilekha Samanta, Santanu Sarkar
A 10-bit 500 MSPS Segmented CS-DAC of > 77 dB SFDR upto the Nyquist with Hexa-decal biasing. VDAT (2020)
Smrutilekha Samanta, Bhawna Tiwari, Pydi Ganga Bahubalindruni, Pedro Barquinha, João Goes
Threshold voltage extraction techniques adaptable from sub-micron CMOS to large-area oxide TFT technologies. Int. J. Circuit Theory Appl. 45 (12) (2017)