Santanu Sarkar

Publication Activity (10 Years)

Years Active: 2016-2024
Publications (10 Years): 7

Top Topics

Memory Efficient

Countermeasures

Top Venues

IACR Cryptol. ePrint Arch.

Int. J. Circuit Theory Appl.

Publications

Smrutilekha Samanta, Santanu Sarkar
Mismatch error compensation of hybrid CS-DAC to achieve high figure of merit utilizing on-chip self-healing assisted swap-enabled randomization technique. Int. J. Circuit Theory Appl. 52 (5) (2024)
Andre Esser, Rahul Girme, Arindam Mukherjee, Santanu Sarkar
Memory-Efficient Attacks on Small LWE Keys. IACR Cryptol. ePrint Arch. 2023 (2023)
Soumya Sahoo, Debasmita Chakraborty, Santanu Sarkar
Unleashing the Power of Differential Fault Attacks on QARMAv2. IACR Cryptol. ePrint Arch. 2023 (2023)
I-Fei Chen, Pi-Ying Kuo, Ruey-Chyn Tsaur, Santanu Sarkar, Shih-Chun Huang
Risk Analysis of Green Supply Chain Using a Hybrid Multi-Criteria Decision Model: Evidence from Laptop Manufacturer Industry. Axioms 11 (12) (2022)
Smrutilekha Samanta, Santanu Sarkar
A 1.8V 8-Bit 500 MSPS Segmented Current Steering DAC with >66 dB SFDR. ISVLSI (2020)
Smrutilekha Samanta, Santanu Sarkar
A 10-bit 500 MSPS Segmented CS-DAC of > 77 dB SFDR upto the Nyquist with Hexa-decal biasing. VDAT (2020)
Sachin Khandagale, Santanu Sarkar
An 8-bit 500 MSPS segmented current steering DAC using Chinese abacus technique. VDAT (2016)