Uddalak Bhattacharya

Publication Activity (10 Years)

Years Active: 1994-2022
Publications (10 Years): 6

Top Topics

Power Dissipation

Magnetic Recording

Top Venues

IEEE J. Solid State Circuits

Publications

Stafford Hutchins, Jiabo Li, Atresh Sanne, Zhanping Chen, Mohammad M. Hasan, Uddalak Bhattacharya, Eric Karl, Jaydeep P. Kulkarni
A High Output Power 1V Charge Pump and Power Switch for Configurable, In-Field-Programmable Metal eFuse on Intel 4 Logic Technology. VLSI Technology and Circuits (2022)
Arindrajit Ghosh, Uddalak Bhattacharya, Manish Kumar, Swapna Banerjee
8T 1R1W register file in 14 nm FinFET technology. Integr. 70 (2020)
Arindrajit Ghosh, Uddalak Bhattacharya, Swapna Banerjee
Contention free delayed keeper for high density large signal sensing memory compiler. Integr. 62 (2018)
Zhanping Chen, Sarvesh H. Kulkarni, Vincent E. Dorgan, Salil Manohar Rajarshi, Lei Jiang, Uddalak Bhattacharya
1T1R Bit Cell in 14-nm High-Density Metal Fuse Technology for High-Volume Manufacturing and In-Field Programming. IEEE J. Solid State Circuits 52 (4) (2017)
Eric Karl, Zheng Guo, James W. Conary, Jeffrey L. Miller, Yong-Gee Ng, Satyanand Nalam, Daeyeon Kim, John Keane, Xiaofei Wang, Uddalak Bhattacharya, Kevin Zhang
A 0.6 V, 1.5 GHz 84 Mb SRAM in 14 nm FinFET CMOS Technology With Capacitive Charge-Sharing Write Assist Circuitry. IEEE J. Solid State Circuits 51 (1) (2016)
Sarvesh H. Kulkarni, Zhanping Chen, Balaji Srinivasan, M. Brian Pedersen, Uddalak Bhattacharya, Kevin Zhang
A High-Density Metal-Fuse Technology Featuring a 1.6 V Programmable Low-Voltage Bit Cell With Integrated 1 V Charge Pumps in 22 nm Tri-Gate CMOS. IEEE J. Solid State Circuits 51 (4) (2016)
Kyung-Hoae Koo, Liqiong Wei, John Keane, Uddalak Bhattacharya, Eric A. Karl, Kevin Zhang
high density and aging resilient 8T SRAM with 14nm FinFET technology featuring 560mV VMIN with read and write assist. VLSIC (2015)
Eric Karl, Zheng Guo, James W. Conary, Jeffrey L. Miller, Yong-Gee Ng, Satyanand Nalam, Daeyeon Kim, John Keane, Uddalak Bhattacharya, Kevin Zhang
17.1 A 0.6V 1.5GHz 84Mb SRAM design in 14nm FinFET CMOS technology. ISSCC (2015)
Eric Karl, Yih Wang, Yong-Gee Ng, Zheng Guo, Fatih Hamzaoglu, Mesut Meterelliyoz, John Keane, Uddalak Bhattacharya, Kevin Zhang, Kaizad Mistry, Mark Bohr
A 4.6 GHz 162 Mb SRAM Design in 22 nm Tri-Gate CMOS Technology With Integrated Read and Write Assist Circuitry. IEEE J. Solid State Circuits 48 (1) (2013)
Eric Karl, Yih Wang, Yong-Gee Ng, Zheng Guo, Fatih Hamzaoglu, Uddalak Bhattacharya, Kevin Zhang, Kaizad Mistry, Mark Bohr
A 4.6GHz 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active VMIN-enhancing assist circuitry. ISSCC (2012)
Pramod Kolar, Eric Karl, Uddalak Bhattacharya, Fatih Hamzaoglu, Henry Nho, Yong-Gee Ng, Yih Wang, Kevin Zhang
A 32 nm High-k Metal Gate SRAM With Adaptive Dynamic Stability Enhancement for Low-Voltage Operation. IEEE J. Solid State Circuits 46 (1) (2011)
Fatih Hamzaoglu, Yih Wang, Pramod Kolar, Liqiong Wei, Yong-Gee Ng, Uddalak Bhattacharya, Kevin Zhang
Bit Cell Optimizations and Circuit Techniques for Nanoscale SRAM Design. IEEE Des. Test Comput. 28 (1) (2011)
Yih Wang, Uddalak Bhattacharya, Fatih Hamzaoglu, Pramod Kolar, Yong-Gee Ng, Liqiong Wei, Ying Zhang, Kevin Zhang, Mark Bohr
A 4.0 GHz 291 Mb Voltage-Scalable SRAM Design in a 32 nm High-k + Metal-Gate CMOS Technology With Integrated Power Management. IEEE J. Solid State Circuits 45 (1) (2010)
Hyunwoo Nho, Pramod Kolar, Fatih Hamzaoglu, Yih Wang, Eric Karl, Yong-Gee Ng, Uddalak Bhattacharya, Kevin Zhang
A 32nm High-k metal gate SRAM with adaptive dynamic stability enhancement for low-voltage operation. ISSCC (2010)
Fatih Hamzaoglu, Kevin Zhang, Yih Wang, Hong Jo Ahn, Uddalak Bhattacharya, Zhanping Chen, Yong-Gee Ng, Andrei Pavlov, Ken Smits, Mark Bohr
A 3.8 GHz 153 Mb SRAM Design With Dynamic Stability Enhancement and Leakage Reduction in 45 nm High-k Metal Gate CMOS Technology. IEEE J. Solid State Circuits 44 (1) (2009)
Yih Wang, Uddalak Bhattacharya, Fatih Hamzaoglu, Pramod Kolar, Yong-Gee Ng, Liqiong Wei, Ying Zhang, Kevin Zhang, Mark Bohr
A 4.0 GHz 291Mb voltage-scalable SRAM design in 32nm high-κ metal-gate CMOS with integrated power management. ISSCC (2009)
Yih Wang, Hong Jo Ahn, Uddalak Bhattacharya, Zhanping Chen, Tom Coan, Fatih Hamzaoglu, Walid M. Hafez, Chia-Hong Jan, Pramod Kolar, Sarvesh H. Kulkarni, Jie-Feng Lin, Yong-Gee Ng, Ian Post, Liqiong Wei, Ying Zhang, Kevin Zhang, Mark Bohr
A 1.1 GHz 12 µA/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications. IEEE J. Solid State Circuits 43 (1) (2008)
Fatih Hamzaoglu, Kevin Zhang, Yih Wang, Hong Jo Ahn, Uddalak Bhattacharya, Zhanping Chen, Yong-Gee Ng, Andrei Pavlov, Ken Smits, Mark Bohr
A 153Mb-SRAM Design with Dynamic Stability Enhancement and Leakage Reduction in 45nm High-Κ Metal-Gate CMOS Technology. ISSCC (2008)
Yih Wang, Hong Jo Ahn, Uddalak Bhattacharya, Tom Coan, Fatih Hamzaoglu, Walid M. Hafez, Chia-Hong Jan, Pramod Kolar, Sarvesh H. Kulkarni, Jie-Feng Lin, Yong-Gee Ng, Ian Post, Liqiong Wei, Yih Zhang, Kevin Zhang, Mark Bohr
A 1.1GHz 12μA/Mb-Leakage SRAM Design in 65nm Ultra-Low-Power CMOS with Integrated Leakage Reduction for Mobile Applications. ISSCC (2007)
Kevin Zhang, Uddalak Bhattacharya, Zhanping Chen, Fatih Hamzaoglu, Daniel Murray, Narendra Vallepalli, Yih Wang, Bo Zheng, Mark Bohr
A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply. IEEE J. Solid State Circuits 41 (1) (2006)
Kevin Zhang, Uddalak Bhattacharya, Zhanping Chen, Fatih Hamzaoglu, Daniel Murray, Narendra Vallepalli, Yih Wang, Bo Zheng, Mark Bohr
SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction. IEEE J. Solid State Circuits 40 (4) (2005)
Cangsang Zhao, Uddalak Bhattacharya, Martin Denham, Jim Kolousek, Yi Lu, Yong-Gee Ng, Novat Nintunze, Kamal Sarkez, Hemmige D. Varadarajan
An 18-Mb, 12.3-GB/s CMOS pipeline-burst cache SRAM with 1.54 Gb/s/pin. IEEE J. Solid State Circuits 34 (11) (1999)
Rajasekhar Pullela, Uddalak Bhattacharya, Scott T. Allen, Mark J. W. Rodwell
Multiplexer/demultiplexer IC technology for 100 Gb/s fiber-optic transmission. IEEE J. Solid State Circuits 31 (5) (1996)
Fleming Hoeg, Stephen I. Long, Uddalak Bhattacharya
Design and performance of multistage GaAs dynamic logic. IEEE J. Solid State Circuits 30 (5) (1995)
Mark J. W. Rodwell, Scott T. Allen, Ruai Y. Yu, Michael G. Case, Uddalak Bhattacharya, Madhukar Reddy, Eric Carman, Masayuki Kamegawa, Yoshiyuki Konishi, Joe Pusl, Rajasekhar Pullela
Active and nonlinear wave propagation devices in ultrafast electronics and optoelectronics. Proc. IEEE 82 (7) (1994)