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A 32nm High-k metal gate SRAM with adaptive dynamic stability enhancement for low-voltage operation.

Hyunwoo NhoPramod KolarFatih HamzaogluYih WangEric KarlYong-Gee NgUddalak BhattacharyaKevin Zhang
Published in: ISSCC (2010)
Keyphrases
  • leakage current
  • low voltage
  • cmos technology
  • power line
  • low power
  • random access memory
  • design considerations
  • power consumption
  • electrical properties
  • image processing
  • power dissipation
  • parallel processing