Satyanand Nalam

Publication Activity (10 Years)

Years Active: 2008-2019
Publications (10 Years): 5

Top Topics

Cmos Technology

Parallel Processing

Top Venues

IEEE J. Solid State Circuits

Publications

Zheng Guo, Daeyeon Kim, Satyanand Nalam, Jami Wiedemer, Xiaofei Wang, Eric Karl
A 23.6-Mb/mm $^{2}$ SRAM in 10-nm FinFET Technology With Pulsed-pMOS TVC and Stepped-WL for Low-Voltage Applications. IEEE J. Solid State Circuits 54 (1) (2019)
Zheng Guo, Daeyeon Kim, Satyanand Nalam, Jami Wiedemer, Xiaofei Wang, Eric Karl
SRAM in 10nm FinFET technology with pulsed PMOS TVC and stepped-WL for low-voltage applications. ISSCC (2018)
Jaydeep P. Kulkarni, John Keane, Kyung-Hoae Koo, Satyanand Nalam, Zheng Guo, Eric Karl, Kevin Zhang
1R1W 8T SRAM Arrays Operating Down to 560 mV Utilizing Small-Signal Sensing With Charge Shared Bitline and Asymmetric Sense Amplifier in 14 nm FinFET CMOS Technology. IEEE J. Solid State Circuits 52 (1) (2017)
John Keane, Jaydeep Kulkarni, Kyung-Hoae Koo, Satyanand Nalam, Zheng Guo, Eric Karl, Kevin Zhang
17.2 5.6Mb/mm2 1R1W 8T SRAM arrays operating down to 560mV utilizing small-signal sensing with charge-shared bitline and asymmetric sense amplifier in 14nm FinFET CMOS technology. ISSCC (2016)
Eric Karl, Zheng Guo, James W. Conary, Jeffrey L. Miller, Yong-Gee Ng, Satyanand Nalam, Daeyeon Kim, John Keane, Xiaofei Wang, Uddalak Bhattacharya, Kevin Zhang
A 0.6 V, 1.5 GHz 84 Mb SRAM in 14 nm FinFET CMOS Technology With Capacitive Charge-Sharing Write Assist Circuitry. IEEE J. Solid State Circuits 51 (1) (2016)
Eric Karl, Zheng Guo, James W. Conary, Jeffrey L. Miller, Yong-Gee Ng, Satyanand Nalam, Daeyeon Kim, John Keane, Uddalak Bhattacharya, Kevin Zhang
17.1 A 0.6V 1.5GHz 84Mb SRAM design in 14nm FinFET CMOS technology. ISSCC (2015)
Sudhanshu Khanna, Satyanand Nalam, Benton H. Calhoun
Pipelined Non-strobed Sensing Scheme for Lowering BL Swing in Nano-scale Memories. VLSI Design (2014)
Satyanand Nalam, Vikas Chandra, Robert C. Aitken, Benton H. Calhoun
Dynamic write limited minimum operating voltage for nanoscale SRAMs. DATE (2011)
Satyanand Nalam, Benton H. Calhoun
5T SRAM With Asymmetric Sizing for Improved Read Stability. IEEE J. Solid State Circuits 46 (10) (2011)
Randy W. Mann, Satyanand Nalam, Jiajing Wang, Benton H. Calhoun
Limits of bias based assist methods in nano-scale 6T SRAM. ISQED (2010)
Satyanand Nalam, Mudit Bhargava, Ken Mai, Benton H. Calhoun
Virtual prototyper (ViPro): an early design space exploration and optimization tool for SRAM designers. DAC (2010)
Satyanand Nalam, Vikas Chandra, Cezary Pietrzyk, Robert C. Aitken, Benton H. Calhoun
Asymmetric 6T SRAM with two-phase write and split bitline differential sensing for low voltage operation. ISQED (2010)
Jiajing Wang, Satyanand Nalam, Zhenyu Qi, Randy W. Mann, Mircea R. Stan, Benton H. Calhoun
Improving SRAM Vmin and yield by using variation-aware BTI stress. CICC (2010)
Satyanand Nalam, Mudit Bhargava, Kyle Ringgenberg, Ken Mai, Benton H. Calhoun
A Technology-Agnostic Simulation Environment (TASE) for iterative custom IC design across processes. ICCD (2009)
Satyanand Nalam, Benton H. Calhoun
Asymmetric sizing in a 45nm 5T SRAM to improve read stability over 6T. CICC (2009)
Jiajing Wang, Satyanand Nalam, Benton H. Calhoun
Analyzing static and dynamic write margin for nanometer SRAMs. ISLPED (2008)