Ken Mai

Publication Activity (10 Years)

Years Active: 1999-2023
Publications (10 Years): 21

Top Topics

Field Programmable Gate Array

Statistical Learning

Random Number Generator

Top Venues

IACR Cryptol. ePrint Arch.

Publications

Siddharth Das, McKenzie van der Hagen, Swarali Patil, Cagri Erbagci, Brandon Lucia, Ken Mai
A 10.33 μJ/encryption Homomorphic Encryption Engine in 28nm CMOS with 4096-degree 109-bit Polynomials for Resource-Constrained IoT Clients. ESSCIRC (2023)
Graham Gobieski, Oguz Atli, Cagri Erbagci, Ken Mai, Nathan Beckmann, Brandon Lucia
MANIC: A $19\mu\mathrm{W}$ @ 4MHz, 256 MOPS/mW, RISC-V microcontroller with embedded MRAM main memory and vector-dataflow co-processor in 22nm bulk finFET CMOS. ISCAS (2023)
Larry T. Pileggi, Siyuan Chen, Keshav Harisrikanth, Guanglin Xu, Ken Mai, Franz Franchetti
A High Throughput Hardware Accelerator for FFTW Codelets: A First Look. HPEC (2022)
Elisaweta Masserova, Deepali Garg, Ken Mai, Lawrence T. Pileggi, Vipul Goyal, Bryan Parno
Logic Locking - Connecting Theory and Practice. IACR Cryptol. ePrint Arch. 2022 (2022)
Siyuan Chen, Ken Mai
Towards Specialized Hardware for Learning-based Visual Odometry on the Edge. IROS (2022)
Samuel Pagliarini, Joseph Sweeney, Ken Mai, R. D. Shawn Blanton, Larry T. Pileggi, Subhasish Mitra
Split-Chip Design to Prevent IP Reverse Engineering. IEEE Des. Test 38 (4) (2021)
Prashanth Mohan, Oguz Atli, Joseph Sweeney, Onur O. Kibar, Larry T. Pileggi, Ken Mai
Hardware Redaction via Designer-Directed Fine-Grained eFPGA Insertion. DATE (2021)
Prashanth Mohan, Oguz Atli, Onur O. Kibar, V. Mohammed Zackriya, Larry T. Pileggi, Ken Mai
Top-down Physical Design of Soft Embedded FPGA Fabrics. FPGA (2021)
Prashanth Mohan, Wen Wang, Bernhard Jungk, Ruben Niederhagen, Jakub Szefer, Ken Mai
ASIC Accelerator in 28 nm for the Post-Quantum Digital Signature Scheme XMSS. ICCD (2020)
Prashanth Mohan, Oguz Atli, Onur O. Kibar, Ken Mai
A Top-Down Design Methodology for Synthesizing FPGA Fabrics Using Standard ASIC Flow. FPGA (2020)
Burak Erbagci, Nail Etkin Can Akkaya, Mudit Bhargava, Rachel Dondero, Ken Mai
Secure hardware-entangled field programmable gate arrays. J. Parallel Distributed Comput. 131 (2019)
Burak Erbagci, Nail Etkin Can Akkaya, Cagri Erbagci, Ken Mai
An Inherently Secure FPGA using PUF Hardware-Entanglement and Side-Channel Resistant Logic in 65nm Bulk CMOS. ESSCIRC (2019)
Yu Cai, Yixin Luo, Saugata Ghose, Erich F. Haratsch, Ken Mai, Onur Mutlu
Read Disturb Errors in MLC NAND Flash Memory. CoRR (2018)
Nail Etkin Can Akkaya, Burak Erbagci, Ken Mai
Secure chip odometers using intentional controlled aging. HOST (2018)
Prashanth Mohan, Nail Etkin Can Akkaya, Burak Erbagci, Ken Mai
A compact energy-efficient pseudo-static camouflaged logic family. HOST (2018)
Nail Etkin Can Akkaya, Burak Erbagci, Ken Mai
A secure camouflaged logic family using post-manufacturing programming with a 3.6GHz adder prototype in 65nm CMOS at 1V nominal VDD. ISSCC (2018)
Yu Cai, Saugata Ghose, Yixin Luo, Ken Mai, Onur Mutlu, Erich F. Haratsch
Characterizing, Exploiting, and Mitigating Vulnerabilities in MLC NAND Flash Memory Programming. CoRR (2018)
Yu Cai, Yixin Luo, Erich F. Haratsch, Ken Mai, Saugata Ghose, Onur Mutlu
Experimental Characterization, Optimization, and Recovery of Data Retention Errors in MLC NAND Flash Memory. CoRR (2018)
Yu Cai, Saugata Ghose, Yixin Luo, Ken Mai, Onur Mutlu, Erich F. Haratsch
Vulnerabilities in MLC NAND Flash Memory Programming: Experimental Analysis, Exploits, and Mitigation Techniques. HPCA (2017)
Burak Erbagci, Cagri Erbagci, Nail Etkin Can Akkaya, Ken Mai
A secure camouflaged threshold voltage defined logic family. HOST (2016)
Cagla Cakir, Ron Ho, Jon K. Lexau, Ken Mai
Scalable High-Radix Modular Crossbar Switches. Hot Interconnects (2016)
Yu Cai, Ken Mai, Onur Mutlu
Comparative evaluation of FPGA and ASIC implementations of bufferless and buffered routing algorithms for on-chip networks. ISQED (2015)
Burak Erbagci, Nail Etkin Can Akkaya, Craig Teegarden, Ken Mai
A 275 Gbps AES encryption accelerator using ROM-based S-boxes in 65nm. CICC (2015)
Mudit Bhargava, Ken Mai
A High Reliability PUF Using Hot Carrier Injection Based Response Reinforcement. IACR Cryptol. ePrint Arch. 2015 (2015)
Nail Etkin Can Akkaya, Burak Erbagci, Raymond Carley, Ken Mai
A DPA-resistant self-timed three-phase dual-rail pre-charge logic family. HOST (2015)
Michael Papamichael, Cagla Cakir, Chen Sun, Chia-Hsin Owen Chen, James C. Hoe, Ken Mai, Li-Shiuan Peh, Vladimir Stojanovic
DELPHI: a framework for RTL-based architecture design evaluation using DSENT models. ISPASS (2015)
Cagla Cakir, Ron Ho, Jon K. Lexau, Ken Mai
Modeling and Design of High-Radix On-Chip Crossbar Switches. NOCS (2015)
Mudit Bhargava, Kaship Sheikh, Ken Mai
Robust true random number generator using hot-carrier injection balanced metastable sense amplifiers. HOST (2015)
Burak Erbagci, Fangfei Liu, Cagla Cakir, Nail Etkin Can Akkaya, Ruby B. Lee, Ken Mai
A 32kB secure cache memory with dynamic replacement mapping in 65nm bulk CMOS. A-SSCC (2015)
Burak Erbagci, Mudit Bhargava, Rachel Dondero, Ken Mai
Deeply hardware-entangled reconfigurable logic and interconnect. ReConFig (2015)
Ronald D. Blanton, Xin Li, Ken Mai, Diana Marculescu, Radu Marculescu, Jeyanandh Paramesh, Jeff G. Schneider, Donald E. Thomas
Statistical Learning in Chip (SLIC). ICCAD (2015)
Yu Cai, Yixin Luo, Erich F. Haratsch, Ken Mai, Onur Mutlu
Data retention in MLC NAND flash memory: Characterization, optimization, and recovery. HPCA (2015)
Ramesh Karri, Farinaz Koushanfar, Ozgur Sinanoglu, Yiorgos Makris, Ken Mai, Ahmad-Reza Sadeghi, Swarup Bhunia
Guest Editorial Special Section on Hardware Security and Trust. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34 (6) (2015)
Cagla Cakir, Ron Ho, Jon K. Lexau, Ken Mai
High-efficiency crossbar switches using capacitively coupled signaling. ISLPED (2015)
Ronald D. Blanton, Xin Li, Ken Mai, Diana Marculescu, Radu Marculescu, Jeyanandh Paramesh, Jeff G. Schneider, Donald E. Thomas
SLIC: Statistical learning in chip. ISIC (2014)
Yu Cai, Gulay Yalcin, Onur Mutlu, Erich F. Haratsch, Osman S. Unsal, Adrián Cristal, Ken Mai
Neighbor-cell assisted error correction for MLC NAND flash memories. SIGMETRICS (2014)
Mudit Bhargava, Ken Mai
An efficient reliable PUF-based cryptographic key generator in 65nm CMOS. DATE (2014)
Ben Niewenhuis, Ronald D. Blanton, Mudit Bhargava, Ken Mai
SCAN-PUF: A low overhead Physically Unclonable Function from scan chain power-up states. ITC (2013)
Mudit Bhargava, Ken Mai
A High Reliability PUF Using Hot Carrier Injection Based Response Reinforcement. CHES (2013)
Yu Cai, Onur Mutlu, Erich F. Haratsch, Ken Mai
Program interference in MLC NAND flash memory: Characterization, modeling, and mitigation. ICCD (2013)
Yu Cai, Erich F. Haratsch, Onur Mutlu, Ken Mai
Threshold voltage distribution in MLC NAND flash memory: characterization, analysis, and modeling. DATE (2013)
Jangwoo Kim, Hyunggyun Yang, Mark P. McCartney, Mudit Bhargava, Ken Mai, Babak Falsafi
Building Fast, Dense, Low-Power Caches Using Erasure-Based Inline Multi-bit ECC. PRDC (2013)
Yu Cai, Gulay Yalcin, Onur Mutlu, Erich F. Haratsch, Adrián Cristal, Osman S. Ünsal, Ken Mai
Flash correct-and-refresh: Retention-aware error management for increased flash memory lifetime. ICCD (2012)
Cagla Cakir, Mudit Bhargava, Ken Mai
6T SRAM and 3T DRAM data retention and remanence characterization in 65nm bulk CMOS. CICC (2012)
Yu Cai, Erich F. Haratsch, Onur Mutlu, Ken Mai
Error patterns in MLC NAND flash memory: Measurement, characterization, and analysis. DATE (2012)
Mudit Bhargava, Cagla Cakir, Ken Mai
Reliability enhancement of bi-stable PUFs in 65nm bulk CMOS. HOST (2012)
Eric S. Chung, Michael Papamichael, Gabriel Weisz, James C. Hoe, Ken Mai
Prototype and evaluation of the CoRAM memory architecture for FPGA-based computing. FPGA (2012)
Mudit Bhargava, Cagla Cakir, Ken Mai
Comparison of bi-stable and delay-based Physical Unclonable Functions from measurements in 65nm bulk CMOS. CICC (2012)
Yu Cai, Erich F. Haratsch, Mark P. McCartney, Mudit Bhargava, Ken Mai
FPGA-based nand flash memory error characterization and solid-state drive prototyping platform (abstract only). FPGA (2011)
Eric S. Chung, James C. Hoe, Ken Mai
CoRAM: an in-fabric memory architecture for FPGA-based computing. FPGA (2011)
Yu Cai, Erich F. Haratsch, Mark P. McCartney, Ken Mai
FPGA-Based Solid-State Drive Prototyping Platform. FCCM (2011)
Craig Teegarden, Mudit Bhargava, Ken Mai
Side-channel Attack Resistant ROM-based AES S-Box. HOST (2010)
Eric S. Chung, Peter A. Milder, James C. Hoe, Ken Mai
Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs? MICRO (2010)
Satyanand Nalam, Mudit Bhargava, Ken Mai, Benton H. Calhoun
Virtual prototyper (ViPro): an early design space exploration and optimization tool for SRAM designers. DAC (2010)
Mudit Bhargava, Cagla Cakir, Ken Mai
Attack Resistant Sense Amplifier based PUFs (SA-PUF) with Deterministic and Controllable Reliability of PUF Responses. HOST (2010)
Eric Menendez, Ken Mai
A Comparison of Power-analysis-resistant Digital Circuits. HOST (2010)
Mudit Bhargava, Mark P. McCartney, Alexander Hoefler, Ken Mai
Low-overhead, digital offset compensated, SRAM sense amplifiers. CICC (2009)
Eric S. Chung, Michael Papamichael, Eriko Nurvitadhi, James C. Hoe, Ken Mai, Babak Falsafi
ProtoFlex: Towards Scalable, Full-System Multiprocessor Simulations Using FPGAs. ACM Trans. Reconfigurable Technol. Syst. 2 (2) (2009)
Satyanand Nalam, Mudit Bhargava, Kyle Ringgenberg, Ken Mai, Benton H. Calhoun
A Technology-Agnostic Simulation Environment (TASE) for iterative custom IC design across processes. ICCD (2009)
Eric Menendez, Ken Mai
A High-Performance, Low-Overhead, Power-Analysis-Resistant, Single-Rail Logic Style. HOST (2008)
Umut Arslan, Mark P. McCartney, Mudit Bhargava, Xin Li, Ken Mai, Lawrence T. Pileggi
Variation-tolerant SRAM sense-amplifier timing using configurable replica bitlines. CICC (2008)
Benton H. Calhoun, Yu Cao, Xin Li, Ken Mai, Lawrence T. Pileggi, Rob A. Rutenbar, Kenneth L. Shepard
Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS. Proc. IEEE 96 (2) (2008)
Larry T. Pileggi, Gökçe Keskin, Xin Li, Ken Mai, Jonathan E. Proesel
Mismatch analysis and statistical design at 65 nm and below. CICC (2008)
Eric S. Chung, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi, Ken Mai
A complexity-effective architecture for accelerating full-system multiprocessor simulations using FPGAs. FPGA (2008)
Eric S. Chung, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi, Ken Mai
PROToFLEX: FPGA-accelerated Hybrid Functional Simulator. IPDPS (2007)
Jangwoo Kim, Nikos Hardavellas, Ken Mai, Babak Falsafi, James C. Hoe
Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding. MICRO (2007)
Ken Mai, Ron Ho, Elad Alon, Dean Liu, Younggon Kim, Dinesh Patil, Mark A. Horowitz
Architecture and circuit techniques for a 1.1-GHz 16-kb reconfigurable memory in 0.18-/spl mu/m CMOS. IEEE J. Solid State Circuits 40 (1) (2005)
Ken Mai, Tim Paaske, Nuwan Jayasena, Ron Ho, William J. Dally, Mark Horowitz
Smart Memories: a modular reconfigurable architecture. ISCA (2000)
Ron Ho, Ken Mai, Hema Kapadia, Mark Horowitz
Interconnect scaling implications for CAD. ICCAD (1999)