Rob A. Rutenbar

ORCID

Publication Activity (10 Years)

Years Active: 1981-2024
Publications (10 Years): 23

Top Venues

Publications

Sunwoong Kim, Cameron James Norris, James I. Oelund, Rob A. Rutenbar
Area-Efficient Iterative Logarithmic Approximate Multipliers for IEEE 754 and Posit Numbers. IEEE Trans. Very Large Scale Integr. Syst. 32 (3) (2024)
Adel Ejjeh, Leon Medvinsky, Aaron Councilman, Hemang Nehra, Suraj Sharma, Vikram S. Adve, Luigi Nardi, Eriko Nurvitadhi, Rob A. Rutenbar
HPVM2FPGA: Enabling True Hardware-Agnostic FPGA Programming. ASAP (2022)
Adel Ejjeh, Vikram S. Adve, Rob A. Rutenbar
Studying the Potential of Automatic Optimizations in the Intel FPGA SDK for OpenCL. CoRR (2022)
Adel Ejjeh, Vikram S. Adve, Rob A. Rutenbar
Studying the Potential of Automatic Optimizations in the Intel FPGA SDK for OpenCL. FPGA (2020)
Glenn G. Ko, Yuji Chai, Marco Donato, Paul N. Whatmough, Thierry Tambe, Rob A. Rutenbar, Gu-Yeon Wei, David Brooks
A Scalable Bayesian Inference Accelerator for Unsupervised Learning. Hot Chips Symposium (2020)
Glenn G. Ko, Yuji Chai, Marco Donato, Paul N. Whatmough, Thierry Tambe, Rob A. Rutenbar, David Brooks, Gu-Yeon Wei
Programmable Bayesian Inference Accelerator for Unsupervised Machine Perception using Parallel Gibbs Sampling in 16nm. VLSI Circuits (2020)
Sunwoong Kim, Keewoo Lee, Wonhee Cho, Yujin Nam, Jung Hee Cheon, Rob A. Rutenbar
Hardware Architecture of a Number Theoretic Transform for a Bootstrappable RNS-based Homomorphic Encryption Scheme. FCCM (2020)
Sunwoong Kim, Rob A. Rutenbar
An Area-Efficient Iterative Single-Precision Floating-Point Multiplier Architecture for FPGA. ACM Great Lakes Symposium on VLSI (2019)
Glenn G. Ko, Yuji Chai, Rob A. Rutenbar, David Brooks, Gu-Yeon Wei
Accelerating Bayesian Inference on Structured Graphs Using Parallel Gibbs Sampling. FPL (2019)
Sunwoong Kim, Keewoo Lee, Wonhee Cho, Jung Hee Cheon, Rob A. Rutenbar
FPGA-based Accelerators of Fully Pipelined Modular Multipliers for Homomorphic Encryption. ReConFig (2019)
Tianqi Gao, Rob A. Rutenbar
A Pixel-Parallel Virtual-Image Architecture for High Performance and Power Efficient Graph Cuts Inference. FPGA (2019)
Glenn G. Ko, Yuji Chai, Rob A. Rutenbar, David Brooks, Gu-Yeon Wei
FlexGibbs: Reconfigurable Parallel Gibbs Sampling Accelerator for Structured Graphs. FCCM (2019)
Tianqi Gao, Rob A. Rutenbar
A Virtual Image Accelerator for Graph Cuts Inference on FPGA. ASAP (2019)
Francine Berman, Rob A. Rutenbar, Brent Hailpern, Henrik Christensen, Susan Davidson, Deborah Estrin, Michael J. Franklin, Margaret Martonosi, Padma Raghavan, Victoria Stodden, Alexander S. Szalay
Realizing the potential of data science. Commun. ACM 61 (4) (2018)
Glenn G. Ko, Rob A. Rutenbar
Real-Time and Low-Power Streaming Source Separation Using Markov Random Field. ACM J. Emerg. Technol. Comput. Syst. 14 (2) (2018)
Sunwoong Kim, Rob A. Rutenbar
Accelerator Design with Effective Resource Utilization for Binary Convolutional Neural Networks on an FPGA. FCCM (2018)
Glenn G. Ko, Rob A. Rutenbar
A case study of machine learning hardware: Real-time source separation using Markov Random Fields via sampling-based inference. ICASSP (2017)
Tianqi Gao, Jungwook Choi, Shang-nien Tsai, Rob A. Rutenbar
Toward a pixel-parallel architecture for graph cuts inference on FPGA. FPL (2017)
Jungwook Choi, Ameya D. Patil, Rob A. Rutenbar, Naresh R. Shanbhag
Analysis of error resiliency of belief propagation in computer vision. ICASSP (2016)
Eric P. Kim, Jungwook Choi, Naresh R. Shanbhag, Rob A. Rutenbar
Error Resilient and Energy Efficient MRF Message-Passing-Based Stereo Matching. IEEE Trans. Very Large Scale Integr. Syst. 24 (3) (2016)
Jungwook Choi, Rob A. Rutenbar
Video-Rate Stereo Matching Using Markov Random Field TRW-S Inference on a Hybrid CPU+FPGA Computing Platform. IEEE Trans. Circuits Syst. Video Technol. 26 (2) (2016)
Jungwook Choi, Rob A. Rutenbar
Configurable and scalable belief propagation accelerator for computer vision. FPL (2016)
Rob A. Rutenbar
Keynote address Wednesday: Hardware inference accelerators for machine learning. ITC (2016)
Skand Hurkat, Jungwook Choi, Eriko Nurvitadhi, José F. Martínez, Rob A. Rutenbar
Fast hierarchical implementation of sequential tree-reweighted belief propagation for probabilistic inference. FPL (2015)
Rob A. Rutenbar
Analog Circuit and Layout Synthesis Revisited. ISPD (2015)
Rob A. Rutenbar
DAC at 50: The Second 25 Years. IEEE Des. Test 31 (2) (2014)
Eric P. Kim, Jungwook Choi, Naresh R. Shanbhag, Rob A. Rutenbar
A robust message passing based stereo matching kernel via system-level error resiliency. ICASSP (2014)
Abner Guzmán-Rivera, Pushmeet Kohli, Dhruv Batra, Rob A. Rutenbar
Efficiently Enforcing Diversity in Multi-Output Structured Prediction. AISTATS (2014)
Rob A. Rutenbar
The First EDA MOOC: Teaching Design Automation to Planet Earth. DAC (2014)
Jungwook Choi, Rob A. Rutenbar
Video-rate stereo matching using markov random field TRW-S inference on a hybrid CPU+FPGA computing platform. FPGA (2013)
Jungwook Choi, Rob A. Rutenbar
FPGA acceleration of Markov Random Field TRW-S inference for stereo matching. MEMOCODE (2013)
Wangyang Zhang, Xin Li, Sharad Saxena, Andrzej J. Strojwas, Rob A. Rutenbar
Automatic clustering of wafer spatial signatures. DAC (2013)
Chuanjun Zhang, Glenn G. Ko, Jungwook Choi, Shang-nien Tsai, Minje Kim, Abner Guzmán-Rivera, Rob A. Rutenbar, Paris Smaragdis, Mi Sun Park, Vijaykrishnan Narayanan, Hongyi Xin, Onur Mutlu, Bin Li, Li Zhao, Mei Chen
EMERALD: Characterization of emerging applications and algorithms for low-power devices. ISPASS (2013)
Wangyang Zhang, Karthik Balakrishnan, Xin Li, Duane S. Boning, Sharad Saxena, Andrzej J. Strojwas, Rob A. Rutenbar
Efficient Spatial Pattern Analysis for Variation Decomposition Via Robust Sparse Regression. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (7) (2013)
Jungwook Choi, Eric P. Kim, Rob A. Rutenbar, Naresh R. Shanbhag
Error resilient MRF message passing architecture for stereo matching. SiPS (2013)
Minje Kim, Paris Smaragdis, Glenn G. Ko, Rob A. Rutenbar
Stereophonic spectrogram segmentation using Markov random fields. MLSP (2012)
Jeffrey R. Johnston, Rob A. Rutenbar
A High-Rate, Low-Power, ASIC Speech Decoder Using Finite State Transducers. ASAP (2012)
Jungwook Choi, Rob A. Rutenbar
Hardware implementation of MRF map inference on an FPGA platform. FPL (2012)
Wangyang Zhang, Karthik Balakrishnan, Xin Li, Duane S. Boning, Emrah Acar, Frank Liu, Rob A. Rutenbar
Spatial variation decomposition via sparse regression. ICICDT (2012)
Wangyang Zhang, Karthik Balakrishnan, Xin Li, Duane S. Boning, Rob A. Rutenbar
Toward efficient spatial variation decomposition via sparse regression. ICCAD (2011)
Wangyang Zhang, Xin Li, Frank Liu, Emrah Acar, Rob A. Rutenbar, Ronald D. Blanton
Virtual Probe: A Statistical Framework for Low-Cost Silicon Characterization of Nanoscale Integrated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (12) (2011)
Wangyang Zhang, Xin Li, Emrah Acar, Frank Liu, Rob A. Rutenbar
Multi-Wafer Virtual Probe: Minimum-cost variation characterization by exploring wafer-to-wafer correlation. ICCAD (2010)
Amith Singhee, Rob A. Rutenbar
Why Quasi-Monte Carlo is Better Than Monte Carlo or Latin Hypercube Sampling for Statistical Circuit Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (11) (2010)
Wangyang Zhang, Xin Li, Rob A. Rutenbar
Bayesian virtual probe: minimizing variation characterization cost for nanoscale IC technologies via Bayesian inference. DAC (2010)
Jiajing Wang, Amith Singhee, Rob A. Rutenbar, Benton H. Calhoun
Two Fast Methods for Estimating the Minimum Standby Supply Voltage for Large SRAMs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (12) (2010)
Rob A. Rutenbar
Analog layout synthesis: what's missing? ISPD (2010)
Patrick Groeneveld, Rob A. Rutenbar, Jed W. Pitera, Erik C. Carlson, Jinsong Chen
Oil fields, hedge funds, and drugs. DAC (2009)
Edward C. Lin, Rob A. Rutenbar
A multi-fpga 10x-real-time high-speed search engine for a 5000-word vocabulary speech recognizer. FPGA (2009)
Kai Yu, Rob A. Rutenbar
Profiling large-vocabulary continuous speech recognition on embedded devices: a hardware resource sensitivity analysis. INTERSPEECH (2009)
Amith Singhee, Rob A. Rutenbar
Statistical Blockade: Very Fast Statistical Simulation and Modeling of Rare Circuit Events and Its Application to Memory Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28 (8) (2009)
Xin Li, Rob A. Rutenbar, R. D. (Shawn) Blanton
Virtual probe: A statistically optimal framework for minimum-cost silicon characterization of nanoscale integrated circuits. ICCAD (2009)
Amith Singhee, Claire Fang Fang, James D. Ma, Rob A. Rutenbar
Probabilistic Interval-Valued Computation: Toward a Practical Surrogate for Statistics Inside CAD Tools. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (12) (2008)
Amith Singhee, Jiajing Wang, Benton H. Calhoun, Rob A. Rutenbar
Recursive Statistical Blockade: An Enhanced Technique for Rare Event Simulation with Application to SRAM Circuit Design. VLSI Design (2008)
Andreas Kuehlmann, Anjan Bose, David E. Corman, Rob A. Rutenbar, Robert M. Manning, Anna Newman
Verifying really complex systems: on earth and beyond. DAC (2008)
Patrick J. Bourke, Rob A. Rutenbar
A low-power hardware search architecture for speech recognition. INTERSPEECH (2008)
Benton H. Calhoun, Yu Cao, Xin Li, Ken Mai, Lawrence T. Pileggi, Rob A. Rutenbar, Kenneth L. Shepard
Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS. Proc. IEEE 96 (2) (2008)
Amith Singhee, Sonia Singhal, Rob A. Rutenbar
Exploiting Correlation Kernels for Efficient Handling of Intra-Die Spatial Correlation, with Application to Statistical Timing. DATE (2008)
Amith Singhee, Sonia Singhal, Rob A. Rutenbar
Practical, fast Monte Carlo statistical static timing analysis: why and how. ICCAD (2008)
Amith Singhee, Rob A. Rutenbar
Statistical blockade: a novel method for very fast Monte Carlo simulation of rare circuit events, and its application. DATE (2007)
Rob A. Rutenbar, Georges G. E. Gielen, Jaijeet S. Roychowdhury
Hierarchical Modeling, Optimization, and Synthesis for System-Level Analog and RF Designs. Proc. IEEE 95 (3) (2007)
Amith Singhee, Rob A. Rutenbar
From Finance to Flip Flops: A Study of Fast Quasi-Monte Carlo Methods from Computational Finance Applied to Statistical Circuit Analysis. ISQED (2007)
Rob A. Rutenbar
Next-Generation Design and EDA Challenges: Small Physics, Big Systems, and Tall Tool-Chains. ASP-DAC (2007)
James D. Ma, Rob A. Rutenbar
Interval-Valued Reduced-Order Statistical Interconnect Modeling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (9) (2007)
Alex K. Jones, Steven P. Levitan, Rob A. Rutenbar, Yuan Xie
Collaborative VLSI-CAD Instruction in the Digital Sandbox. MSE (2007)
Kai Yu, Rob A. Rutenbar
Generating small, accurate acoustic models with a modified Bayesian information criterion. INTERSPEECH (2007)
Edward C. Lin, Kai Yu, Rob A. Rutenbar, Tsuhan Chen
A 1000-word vocabulary, speaker-independent, continuous live-mode speech recognizer implemented in a single FPGA. FPGA (2007)
Yu-Tsun Chien, Dong Chen, Jea-Hong Lou, Gin-Kou Ma, Rob A. Rutenbar, Tamal Mukherjee
Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters CoRR (2007)
Jiajing Wang, Amith Singhee, Rob A. Rutenbar, Benton H. Calhoun
Statistical modeling for the minimum standby supply voltage of a full SRAM array. ESSCIRC (2007)
Amith Singhee, Rob A. Rutenbar
Beyond Low-Order Statistical Response Surfaces: Latent Variable Regression for Efficient, Highly Nonlinear Fitting. DAC (2007)
Zhong Xiu, Rob A. Rutenbar
Mixed-size placement with fixed macrocells using grid-warping. ISPD (2007)
Saurabh K. Tiwary, Rob A. Rutenbar
On-the-Fly Fidelity Assessment for Trajectory-Based Circuit Macromodels. CICC (2006)
Goran Frehse, Bruce H. Krogh, Rob A. Rutenbar, Oded Maler
Time Domain Verification of Oscillator Circuit Properties. Electron. Notes Theor. Comput. Sci. 153 (3) (2006)
Amith Singhee, Claire Fang Fang, James D. Ma, Rob A. Rutenbar
Probabilistic interval-valued computation: toward a practical surrogate for statistics inside CAD tools. DAC (2006)
Goran Frehse, Bruce H. Krogh, Rob A. Rutenbar
Verifying analog oscillator circuits using forward/backward abstraction refinement. DATE (2006)
Edward C. Lin, Kai Yu, Rob A. Rutenbar, Tsuhan Chen
In silico vox: Towards speech recognition in silicon. Hot Chips Symposium (2006)
Rob A. Rutenbar
Design automation for analog: the next generation of tool challenges. ICCAD (2006)
Saurabh K. Tiwary, Rob A. Rutenbar
Faster, parametric trajectory-based macromodels via localized linear reductions. ICCAD (2006)
Saurabh K. Tiwary, Pragati K. Tiwary, Rob A. Rutenbar
Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration. DAC (2006)
Edward C. Lin, Kai Yu, Rob A. Rutenbar, Tsuhan Chen
Moving speech recognition from software to silicon: the in silico vox project. INTERSPEECH (2006)
James D. Ma, Rob A. Rutenbar
Fast Interval-Valued Statistical Modeling of Interconnect and Effective Capacitance. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (4) (2006)
James D. Ma, Claire Fang Fang, Rob A. Rutenbar, Xiaolin Xie, Duane S. Boning
Interval-valued statistical modeling of oxide chemical-mechanical polishing. ICCAD (2005)
James D. Z. Ma, Rob A. Rutenbar
Fast interval-valued statistical interconnect modeling and reduction. ISPD (2005)
Zhong Xiu, David A. Papa, Philip Chong, Christoph Albrecht, Andreas Kuehlmann, Rob A. Rutenbar, Igor L. Markov
Early research experience with OpenAccess gear: an open source development environment for physical design. ISPD (2005)
Saurabh K. Tiwary, Rob A. Rutenbar
Scalable trajectory methods for on-demand analog macromodel extraction. DAC (2005)
Yu-Tsun Chien, Dong Chen, Jea-Hong Lou, Gin-Kou Ma, Rob A. Rutenbar, Tamal Mukherjee
Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters. DATE (2005)
Zhong Xiu, Rob A. Rutenbar
Timing-driven placement by grid-warping. DAC (2005)
Zhong Xiu, James D. Z. Ma, Suzanne M. Fowler, Rob A. Rutenbar
Large-scale placement by grid-warping. DAC (2004)
Rob A. Rutenbar, Anthony R. Bonaccio, Teresa H. Meng, Ernesto Perea, Robert Pitts, Charles G. Sodini, Jim Wieser
Will Moore's Law rule in the land of analog? DAC (2004)
Gi-Joon Nam, Fadi A. Aloul, Karem A. Sakallah, Rob A. Rutenbar
A Comparative Study of Two Boolean Formulations of FPGA Detailed Routing Constraints. IEEE Trans. Computers 53 (6) (2004)
Gang Zhang, E. Aykut Dengi, Ronald A. Rohrer, Rob A. Rutenbar, L. Richard Carley
A synthesis flow toward fast parasitic closure for radio-frequency integrated circuits. DAC (2004)
Rob A. Rutenbar, Li-C. Wang, Kwang-Ting Cheng, Sandip Kundu
Static statistical timing analysis for latch-based pipeline designs. ICCAD (2004)
Smriti Gupta, Bruce H. Krogh, Rob A. Rutenbar
Towards formal verification of analog designs. ICCAD (2004)
James D. Ma, Rob A. Rutenbar
Interval-valued reduced order statistical interconnect modeling. ICCAD (2004)
Claire Fang Fang, Tsuhan Chen, Rob A. Rutenbar
Floating-point error analysis based on affine arithmetic. ICASSP (2) (2003)
Claire Fang Fang, Rob A. Rutenbar, Tsuhan Chen
Fast, Accurate Static Analysis for Fixed-Point Finite-Precision Effects in DSP Designs. ICCAD (2003)
Claire Fang Fang, Rob A. Rutenbar, Markus Püschel, Tsuhan Chen
Toward efficient static analysis of finite-precision effects in DSP applications via affine arithmetic modeling. DAC (2003)
Rob A. Rutenbar, David L. Harame, Kurt Johnson, Paul Kempf, Teresa H. Meng, Reza Rofougaran, James Spoto
Mixed signals on mixed-signal: the right next technology. DAC (2003)
Hui Xu, Rob A. Rutenbar, Karem A. Sakallah
sub-SAT: a formulation for relaxed Boolean satisfiability with applications in routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22 (6) (2003)
Claire Fang Fang, Tsuhan Chen, Rob A. Rutenbar
Lightweight Floating-Point Arithmetic: Case Study of Inverse Discrete Cosine Transform. EURASIP J. Adv. Signal Process. 2002 (9) (2002)
Gi-Joon Nam, Karem A. Sakallah, Rob A. Rutenbar
Hybrid Routing for FPGAs by Integrating Boolean Satisfiability with Geometric Search. FPL (2002)

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Publication Activity (10 Years)

Top Topics

Top Venues

Rob A. Rutenbar