R. D. (Shawn) Blanton

Publication Activity (10 Years)

Years Active: 1996-2023
Publications (10 Years): 19

Top Topics

Axiomatic Characterization

Feature Reduction

Top Venues

ACM Trans. Design Autom. Electr. Syst.

Publications

Wei Li, Fangzhou Wang, José M. F. Moura, R. D. (Shawn) Blanton
Global Floorplanning via Semidefinite Programming. DAC (2023)
Qicheng Huang, Chenlei Fang, Soumya Mittal, R. D. (Shawn) Blanton
Towards Smarter Diagnosis: A Learning-based Diagnostic Outcome Previewer. ACM Trans. Design Autom. Electr. Syst. 25 (5) (2020)
Ruizhou Ding, Zeye Liu, Ting-Wu Chin, Diana Marculescu, R. D. (Shawn) Blanton
FLightNNs: Lightweight Quantized Deep Neural Networks for Fast and Accurate Inference. DAC (2019)
Zeye Liu, Qicheng Huang, Chenlei Fang, R. D. (Shawn) Blanton
Improving Test Chip Design Efficiency via Machine Learning. ITC (2019)
Danielle Duvalsaint, Xiaoxiao Jin, Benjamin Niewenhuis, R. D. (Shawn) Blanton
Characterization of Locked Combinational Circuits via ATPG. ITC (2019)
Soumya Mittal, R. D. (Shawn) Blanton
NOIDA: Noise-resistant Intra-cell Diagnosis. VTS (2018)
Ruizhou Ding, Zeye Liu, R. D. (Shawn) Blanton, Diana Marculescu
Lightening the Load with Highly Accurate Storage- and Energy-Efficient LightNNs. ACM Trans. Reconfigurable Technol. Syst. 11 (3) (2018)
Ruizhou Ding, Zeye Liu, R. D. (Shawn) Blanton, Diana Marculescu
Quantized deep neural networks for energy efficient hardware-based inference. ASP-DAC (2018)
Ruizhou Ding, Zeye Liu, Rongye Shi, Diana Marculescu, R. D. (Shawn) Blanton
LightNN: Filling the Gap between Conventional Deep Neural Networks and Binarized Networks. CoRR (2018)
Xuanle Ren, R. D. (Shawn) Blanton, Vítor Grade Tavares
Detection of IJTAG attacks using LDPC-based feature reduction and machine learning. ETS (2018)
Cheng Xue, R. D. (Shawn) Blanton
Test-set reordering for improving diagnosability. VTS (2017)
Ben Niewenhuis, Soumya Mittal, R. D. (Shawn) Blanton
Multiple-defect diagnosis for Logic Characterization Vehicles. ETS (2017)
Soumya Mittal, R. D. (Shawn) Blanton
PADLOC: Physically-Aware Defect Localization and Characterization. ATS (2017)
Xiang Lin, R. D. (Shawn) Blanton, Donald E. Thomas
Random Forest Architectures on FPGA for Multiple Applications. ACM Great Lakes Symposium on VLSI (2017)
Ruizhou Ding, Zeye Liu, Rongye Shi, Diana Marculescu, R. D. (Shawn) Blanton
LightNN: Filling the Gap between Conventional Deep Neural Networks and Binarized Networks. ACM Great Lakes Symposium on VLSI (2017)
Soumya Mittal, Zeye Liu, Ben Niewenhuis, R. D. (Shawn) Blanton
Test chip design for optimal cell-aware diagnosability. ITC (2016)
Hongfei Wang, R. D. (Shawn) Blanton
Ensemble Reduction via Logic Minimization. ACM Trans. Design Autom. Electr. Syst. 21 (4) (2016)
Zeye Liu, Ben Niewenhuis, Soumya Mittal, R. D. (Shawn) Blanton
Achieving 100% cell-aware coverage by design. DATE (2016)
Phillip Fynan, Zeye Liu, Benjamin Niewenhuis, Soumya Mittal, Marcin Strajwas, R. D. (Shawn) Blanton
Logic characterization vehicle design reflection via layout rewiring. ITC (2016)
R. D. (Shawn) Blanton, Benjamin Niewenhuis, Zeye (Dexter) Liu
Design reflection for optimal test-chip implementation. ITC (2015)
Cheng Xue, R. D. (Shawn) Blanton
A one-pass test-selection method for maximizing test coverage. ICCD (2015)
Xuanle Ren, Vítor Grade Tavares, R. D. (Shawn) Blanton
Detection of illegitimate access to JTAG via statistical learning in chip. DATE (2015)
John A. Porche, R. D. (Shawn) Blanton
Physically-Aware Diagnostic Resolution. ATS (2014)
Sounil Biswas, Hongfei Wang, R. D. (Shawn) Blanton
Reducing test cost of integrated, heterogeneous systems using pass-fail test data analysis. ACM Trans. Design Autom. Electr. Syst. 19 (2) (2014)
Wing Chiu Tam, R. D. (Shawn) Blanton
Design-for-Manufacturability Assessment for Integrated Circuits Using RADAR. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (10) (2014)
Cheng Xue, R. D. (Shawn) Blanton
Predicting IC Defect Level Using Diagnosis. ATS (2014)
Matthew Beckler, R. D. (Shawn) Blanton
On-chip diagnosis for early-life and wear-out failures. ITC (2012)
Yen-Tzu Lin, Osei Poku, R. D. (Shawn) Blanton, Phil Nigh, Peter Lloyd, Vikram Iyengar
Physically-Aware N-Detect Test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (2) (2012)
R. D. (Shawn) Blanton, Wing Chiu Tam, Xiaochun Yu, Jeffrey E. Nelson, Osei Poku
Yield Learning Through Physically Aware Diagnosis of IC-Failure Populations. IEEE Des. Test Comput. 29 (1) (2012)
Wing Chiu Tam, R. D. (Shawn) Blanton
SLIDER: Simulation of Layout-Injected Defects for Electrical Responses. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (6) (2012)
Xiaochun Yu, R. D. (Shawn) Blanton
Diagnosis-Assisted Adaptive Test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (9) (2012)
Wing Chiu Tam, R. D. (Shawn) Blanton
To DFM or not to DFM? DAC (2011)
Yen-Tzu Lin, R. D. (Shawn) Blanton
METER: Measuring Test Effectiveness Regionally. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (7) (2011)
Xiaochun Yu, R. D. (Shawn) Blanton
Statistical defect-detection analysis of test sets using readily-available tester data. ICCAD (2011)
Wing Chiu Tam, R. D. (Shawn) Blanton
Physically-aware analysis of systematic defects in integrated circuits. ITC (2011)
Wing Chiu Tam, R. D. (Shawn) Blanton, Wojciech Maly
Evaluating yield and testing impact of sub-wavelength lithography. VTS (2010)
Wing Chiu Tam, Osei Poku, R. D. (Shawn) Blanton
Automated failure population creation for validating integrated circuit diagnosis methods. DAC (2009)
Xin Li, Rob A. Rutenbar, R. D. (Shawn) Blanton
Virtual probe: A statistically optimal framework for minimum-cost silicon characterization of nanoscale integrated circuits. ICCAD (2009)
Wing Chiu Tam, Osei Poku, R. D. (Shawn) Blanton
Precise failure localization using automated layout analysis of diagnosis candidates. DAC (2008)
Xiaochun Yu, R. D. (Shawn) Blanton
Multiple defect diagnosis using no assumptions on failing pattern characteristics. DAC (2008)
Jason G. Brown, R. D. (Shawn) Blanton
Automated Standard Cell Library Analysis for Improved Defect Modeling. ISQED (2008)
Sounil Biswas, R. D. (Shawn) Blanton
Test Compaction for Mixed-Signal Circuits Using Pass-Fail Test Data. VTS (2008)
Jason G. Brown, R. D. (Shawn) Blanton
A Built-in Self-test and Diagnosis Strategy for Chemically Assembled Electronic Nanotechnology. J. Electron. Test. 23 (2-3) (2007)
Sounil Biswas, Peng Li, R. D. (Shawn) Blanton, Larry T. Pileggi
Specification Test Compaction for Analog Circuits and MEMS CoRR (2007)
Jeffrey E. Nelson, Thomas Zanon, Jason G. Brown, Osei Poku, R. D. (Shawn) Blanton, Wojciech Maly, Brady Benware, Chris Schuermyer
Extracting Defect Density and Size Distributions from Product ICs. IEEE Des. Test Comput. 23 (5) (2006)
Jeffrey E. Nelson, Thomas Zanon, Rao Desineni, Jason G. Brown, N. Patil, Wojciech Maly, R. D. (Shawn) Blanton
Extraction of defect density and size distributions from wafer sort test results. DATE (2006)
Jason G. Brown, R. D. (Shawn) Blanton
Exploiting Regularity for Inductive Fault Analysis. VTS (2006)
Jeffrey E. Nelson, Jason G. Brown, Rao Desineni, R. D. (Shawn) Blanton
Multiple-detect ATPG based on physical neighborhoods. DAC (2006)
Tao Jiang, R. D. (Shawn) Blanton
Inductive fault analysis of surface-micromachined MEMS. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (6) (2006)
Rao Desineni, R. D. (Shawn) Blanton
Diagnosis of Arbitrary Defects Using Neighborhood Function Extraction. VTS (2005)
Sounil Biswas, Peng Li, R. D. (Shawn) Blanton, Larry T. Pileggi
Specification Test Compaction for Analog Circuits and MEMS. DATE (2005)
R. D. (Shawn) Blanton, Subhasish Mitra
Testing Nanometer Digital Integration Circuits: Myths, Reality and the Road Ahead. VLSI Design (2005)
Sounil Biswas, Kumar N. Dwarakanath, R. D. (Shawn) Blanton
Generalized Sensitization using Fault Tuples. VTS (2004)
Thomas J. Vogels, Thomas Zanon, Rao Desineni, R. D. (Shawn) Blanton, Wojciech Maly, Jason G. Brown, Jeffrey E. Nelson, Y. Fei, X. Huang, Padmini Gopalakrishnan, Mahim Mishra, Vyacheslav Rovner, S. Tiwary
Benchmarking Diagnosis Algorithms With a Diverse Set of IC Deformations. ITC (2004)
Nilmoni Deb, R. D. (Shawn) Blanton
Multi-Modal Built-In Self-Test for Symmetric Microsystems. VTS (2004)
Jason G. Brown, R. D. (Shawn) Blanton
CAEN-BIST: Testing the NanoFabric. ITC (2004)
R. D. (Shawn) Blanton, Kumar N. Dwarakanath, Anirudh B. Shah
Analyzing the Effectiveness of Multiple-Detect Test Sets. ITC (2003)
Wojciech Maly, Anne E. Gattiker, Thomas Zanon, Thomas J. Vogels, R. D. (Shawn) Blanton, Thomas M. Storey
Deformations of IC Structure in Test and Yield Learning. ITC (2003)
Rahul Kundu, R. D. (Shawn) Blanton
ATPG for Noise-Induced Switch Failures in Domino Logic. ICCAD (2003)
Thomas J. Vogels, Wojciech Maly, R. D. (Shawn) Blanton
Progressive Bridge Identification. ITC (2003)
Rahul Kundu, R. D. (Shawn) Blanton
Path Delay Test Generation for Domino Logic Circuits in the Presence of Crosstalk. ITC (2003)
Rahul Kundu, R. D. (Shawn) Blanton
Timed Test Generation Crosstalk Switch Failures in Domino CMOS Circuits. VTS (2002)
Nilmoni Deb, R. D. (Shawn) Blanton
Built-In Self Test of CMOS-MEMS Accelerometers. ITC (2002)
Salvador Mir, H. Bederr, R. D. (Shawn) Blanton, Hans G. Kerkhoff, H. J. Klim
SoCs with MEMS? Can We Include MEMS in the SoCs Design and Test Flow? VTS (2002)
Kumar N. Dwarakanath, R. D. (Shawn) Blanton
Exploiting Dominance and Equivalence using Fault Tuples. VTS (2002)
Keerthi Heragu, Manish Sharma, Rahul Kundu, R. D. (Shawn) Blanton
Testing of Dynamic Logic Circuits Based on Charge Sharing. VTS (2001)
Noppanunt Utamaphethai, R. D. (Shawn) Blanton, John Paul Shen
A Buffer-Oriented Methodology for Microarchitecture Validation. J. Electron. Test. 16 (1-2) (2000)
Noppanunt Utamaphethai, R. D. (Shawn) Blanton, John Paul Shen
Effectiveness of Microarchitecture Test Program Generation. IEEE Des. Test Comput. 17 (4) (2000)
Candice Bechem, Jonathan Combs, Noppanunt Utamaphethai, Bryan Black, R. D. (Shawn) Blanton, John Paul Shen
An integrated functional performance simulator. IEEE Micro 19 (3) (1999)
Tamal Mukherjee, Gary K. Fedder, R. D. (Shawn) Blanton
Hierarchical Design and Test of Integrated Microsystems. IEEE Des. Test Comput. 16 (4) (1999)
Noppanunt Utamaphethai, R. D. (Shawn) Blanton, John Paul Shen
Superscalar Processor Validation at the Microarchitecture Level. VLSI Design (1999)
Bernard Courtois, R. D. (Shawn) Blanton
Guest Editors' Introduction. IEEE Des. Test Comput. 16 (4) (1999)
R. D. (Shawn) Blanton
IDDQ-Testability of Tree Circuits. VLSI Design (1999)
William E. Dougherty, R. D. (Shawn) Blanton
Using regression analysis for GA-based ATPG parameter optimization. ICCD (1998)
R. D. (Shawn) Blanton, John P. Hayes
Testability Properties of Divergent Trees. J. Electron. Test. 11 (3) (1997)
R. D. (Shawn) Blanton, John P. Hayes
Design of a fast, easily testable ALU. VTS (1996)