Vyacheslav Rovner

Publication Activity (10 Years)

Years Active: 2003-2010
Publications (10 Years): 0

Publications

Tejas Jhaveri, Vyacheslav Rovner, Lars Liebmann, Larry T. Pileggi, Andrzej J. Strojwas, Jason Hibbeler
Co-Optimization of Circuits, Layout and Lithography for Predictive Technology Scaling Beyond Gratings. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (4) (2010)
Andrzej J. Strojwas, Tejas Jhaveri, Vyacheslav Rovner, Lawrence T. Pileggi
Creating an affordable 22nm node using design-lithography co-optimization. DAC (2009)
V. Kheterpal, Vyacheslav Rovner, T. G. Hersan, D. Motiani, Y. Takegawa, Andrzej J. Strojwas, Lawrence T. Pileggi
Design methodology for IC manufacturability based on regular logic-bricks. DAC (2005)
Thomas J. Vogels, Thomas Zanon, Rao Desineni, R. D. (Shawn) Blanton, Wojciech Maly, Jason G. Brown, Jeffrey E. Nelson, Y. Fei, X. Huang, Padmini Gopalakrishnan, Mahim Mishra, Vyacheslav Rovner, S. Tiwary
Benchmarking Diagnosis Algorithms With a Diverse Set of IC Deformations. ITC (2004)
Lawrence T. Pileggi, Herman Schmit, Andrzej J. Strojwas, Padmini Gopalakrishnan, V. Kheterpal, Aneesh Koorapaty, Chetan Patel, Vyacheslav Rovner, K. Y. Tong
Exploring regular fabrics to optimize the performance-cost trade-off. DAC (2003)
K. Y. Tong, V. Kheterpal, Vyacheslav Rovner, Lawrence T. Pileggi, Herman Schmit
Regular logic fabrics for a via patterned gate array (VPGA). CICC (2003)