John Paul Shen

Publication Activity (10 Years)

Years Active: 1980-2024
Publications (10 Years): 31

Top Venues

CoRR

ISVLSI

UbiComp/ISWC Adjunct

Frontiers Big Data

Publications

Harideep Nair, David Barajas-Jasso, Quinn Jacobson, John Paul Shen
TNN-CIM: An In-SRAM CMOS Implementation of TNN-Based Synaptic Arrays with STDP Learning. AICAS (2024)
Harideep Nair, William Leyman, Agastya Sampath, Quinn Jacobson, John Paul Shen
NeRTCAM: CAM-Based CMOS Implementation of Reference Frames for Neuromorphic Processors. NICE (2024)
Harideep Nair, William Leyman, Agastya Sampath, Quinn Jacobson, John Paul Shen
NeRTCAM: CAM-Based CMOS Implementation of Reference Frames for Neuromorphic Processors. CoRR (2024)
Prabhu Vellaisamy, Harideep Nair, Vamsikrishna Ratnakaram, Dhruv Gupta, John Paul Shen
TNNGen: Automated Design of Neuromorphic Sensory Processing Units for Time-Series Clustering. IEEE Trans. Circuits Syst. II Express Briefs 71 (5) (2024)
Harideep Nair, Prabhu Vellaisamy, Tsung-Han Lin, Perry H. Wang, Ronald Shawn Blanton, John Paul Shen
OzMAC: An Energy-Efficient Sparsity-Exploiting Multiply-Accumulate-Unit Design for DL Inference. CoRR (2024)
Shanmuga Venkatachalam, Harideep Nair, Ming Zeng, Cathy Tan, Ole J. Mengshoel, John Paul Shen
Corrigendum: SemNet: Learning semantic attributes for human activity recognition with deep belief networks. Frontiers Big Data 6 (2024)
Shanmuga Venkatachalam, Harideep Nair, Prabhu Vellaisamy, Yongqi Zhou, Ziad Youssfi, John Paul Shen
Realtime Person Identification via Gait Analysis. CoRR (2024)
Adeola Bannis, Shijia Pan, Carlos Ruiz Dominguez, John Paul Shen, Hae Young Noh, Pei Zhang
IDIoT: Multimodal Framework for Ubiquitous Identification and Assignment of Human-carried Wearable Devices. ACM Trans. Internet Things 4 (2) (2023)
Prabhu Vellaisamy, Harideep Nair, Joseph Finn, Manav Trivedi, Albert Chen, Anna Li, Tsung-Han Lin, Perry H. Wang, Ronald Shawn Blanton, John Paul Shen
tubGEMM: Energy-Efficient and Sparsity-Effective Temporal-Unary-Binary Based Matrix Multiply Unit. ISVLSI (2023)
Harideep Nair, Prabhu Vellaisamy, Albert Chen, Joseph Finn, Anna Li, Manav Trivedi, John Paul Shen
tuGEMM: Area-Power-Efficient Temporal Unary GEMM Architecture for Low-Precision Edge AI. ISCAS (2023)
Harideep Nair, Prabhu Vellaisamy, Santha Bhasuthkar, John Paul Shen
TNN7: A Custom Macro Suite for Implementing Highly Optimized Designs of Neuromorphic TNNs. CoRR (2022)
Prabhu Vellaisamy, John Paul Shen
Towards a Design Framework for TNN-Based Neuromorphic Sensory Processing Units. CoRR (2022)
Harideep Nair, Prabhu Vellaisamy, Santha Bhasuthkar, John Paul Shen
TNN7: A Custom Macro Suite for Implementing Highly Optimized Designs of Neuromorphic TNNs. ISVLSI (2022)
Shanmuga Venkatachalam, Harideep Nair, Ming Zeng, Cathy Tan, Ole J. Mengshoel, John Paul Shen
SemNet: Learning semantic attributes for human activity recognition with deep belief networks. Frontiers Big Data 5 (2022)
Harideep Nair, John Paul Shen, James E. Smith
A Microarchitecture Implementation Framework for Online Learning with Temporal Neural Networks. ISVLSI (2021)
Shreyas Chaudhari, Harideep Nair, José M. F. Moura, John Paul Shen
Unsupervised Clustering of Time Series Signals Using Neuromorphic Energy-Efficient Temporal Neural Networks. ICASSP (2021)
Harideep Nair, John Paul Shen, James E. Smith
A Microarchitecture Implementation Framework for Online Learning with Temporal Neural Networks. CoRR (2021)
Shreyas Chaudhari, Harideep Nair, José M. F. Moura, John Paul Shen
Unsupervised Clustering of Time Series Signals using Neuromorphic Energy-Efficient Temporal Neural Networks. CoRR (2021)
Tyler Nuanes, Matt Elsey, Radek Grzeszczuk, John Paul Shen
Sky Segmentation for Enhanced Depth Reconstruction and Bokeh Rendering with Efficient Architectures. Computational Imaging (2020)
Harideep Nair, John Paul Shen, James E. Smith
Direct CMOS Implementation of Neuromorphic Temporal Neural Networks for Sensory Processing. CoRR (2020)
Harideep Nair, Prabhu Vellaisamy, Santha Bhasuthkar, John Paul Shen
A Custom 7nm CMOS Standard Cell Library for Implementing TNN-based Neuromorphic Processors. CoRR (2020)
Abhinav Jauhri, Brad Stocks, Jian-Hui Li, Koichi Yamada, John Paul Shen
Generating Realistic Ride-Hailing Datasets Using GANs. ACM Trans. Spatial Algorithms Syst. 6 (3) (2020)
Guan-Lin Chao, Chih Chi Hu, Bing Liu, John Paul Shen, Ian R. Lane
Audio-visual TED corpus: enhancing the TED-LIUM corpus with facial information, contextual text and object recognition. UbiComp/ISWC Adjunct (2019)
Guan-Lin Chao, John Paul Shen, Ian R. Lane
Deep Speaker Embedding for Speaker-Targeted Automatic Speech Recognition. NLPIR (2019)
Harideep Nair, Cathy Tan, Ming Zeng, Ole J. Mengshoel, John Paul Shen
AttriNet: learning mid-level features for human activity recognition with deep belief networks. UbiComp/ISWC Adjunct (2019)
Ming Zeng, Tong Yu, Ole J. Mengshoel, Helen Qin, Chris Lee, John Paul Shen
Improving Bag-Of-Words: Capturing Local Information for Motion-Based Activity Recognition. UbiComp/ISWC Adjunct (2018)
Shijia Pan, Ceferino Gabriel Ramirez, Mostafa Mirshekari, Jonathon Fagert, Albert Jin Chung, Chih Chi Hu, John Paul Shen, Hae Young Noh, Pei Zhang
SurfaceVibe: vibration-based tap & swipe tracking on ubiquitous surfaces. IPSN (2017)
Abhinav Jauhri, Carlee Joe-Wong, John Paul Shen
On the Real-time Vehicle Placement Problem. CoRR (2017)
Abhinav Jauhri, Brian Foo, Jérôme Berclaz, Chih Chi Hu, Radek Grzeszczuk, Vasu Parameswaran, John Paul Shen
Space-Time Graph Modeling of Ride Requests Based on Real-World Data. AAAI Workshops (2017)
Min Hao Chen, Abhinav Jauhri, John Paul Shen
Data Driven Analysis of the Potentials of Dynamic Ride Pooling. IWCTS@SIGSPATIAL (2017)
Abhinav Jauhri, Brian Foo, Jérôme Berclaz, Chih Chi Hu, Radek Grzeszczuk, Vasu Parameswaran, John Paul Shen
Space-Time Graph Modeling of Ride Requests Based on Real-World Data. CoRR (2017)
Carlos Madriles, Carlos García Quiñones, F. Jesús Sánchez, Pedro Marcuello, Antonio González, Dean M. Tullsen, Hong Wang, John Paul Shen
Mitosis: A Speculative Multithreaded Processor Based on Precomputation Slices. IEEE Trans. Parallel Distributed Syst. 19 (7) (2008)
Richard A. Hankins, Gautham N. Chinya, Jamison D. Collins, Perry H. Wang, Ryan N. Rakvic, Hong Wang, John Paul Shen
Multiple Instruction Stream Processor. ISCA (2006)
Bryan Black, Murali Annavaram, Ned Brekelbaum, John DeVale, Lei Jiang, Gabriel H. Loh, Don McCaule, Patrick Morrow, Donald W. Nelson, Daniel Pantuso, Paul Reed, Jeff Rupley, Sadasivan Shankar, John Paul Shen, Clair Webb
Die Stacking (3D) Microarchitecture. MICRO (2006)
Murali Annavaram, Ed Grochowski, John Paul Shen
Mitigating Amdahl's Law through EPI Throttling. ISCA (2005)
Satish Narayanasamy, Hong Wang, Perry H. Wang, John Paul Shen, Brad Calder
A Dependency Chain Clustered Microarchitecture. IPDPS (2005)
Ed Grochowski, Ronny Ronen, John Paul Shen, Hong Wang
Best of Both Latency and Throughput. ICCD (2004)
Perry H. Wang, Jamison D. Collins, Hong Wang, Dongkeun Kim, Bill Greene, Kai-Ming Chan, Aamir B. Yunus, Terry Sych, Stephen F. Moore, John Paul Shen
Helper Threads via Virtual Multithreading. IEEE Micro 24 (6) (2004)
Dongkeun Kim, Shih-Wei Liao, Perry H. Wang, Juan del Cuvillo, Xinmin Tian, Xiang Zou, Hong Wang, Donald Yeung, Milind Girkar, John Paul Shen
Physical Experimentation with Prefetching Helper Threads on Intel's Hyper-Threaded Processors. CGO (2004)
Perry H. Wang, Jamison D. Collins, Hong Wang, Dongkeun Kim, Bill Greene, Kai-Ming Chan, Aamir B. Yunus, Terry Sych, Stephen F. Moore, John Paul Shen
2 processor-based platform. ASPLOS (2004)
Tor M. Aamodt, Paul Chow, Per Hammarlund, Hong Wang, John Paul Shen
Hardware Support for Prescient Instruction Prefetch. HPCA (2004)
Partha Kundu, Murali Annavaram, Trung A. Diep, John Paul Shen
A case for shared instruction cache on chip multiprocessors running OLTP. SIGARCH Comput. Archit. News 32 (3) (2004)
Tor M. Aamodt, Pedro Marcuello, Paul Chow, Antonio González, Per Hammarlund, Hong Wang, John Paul Shen
A framework for modeling and optimization of prescient instruction prefetch. SIGMETRICS (2003)
Richard A. Hankins, Trung A. Diep, Murali Annavaram, Brian Hirano, Harald Eri, Hubert Nueckel, John Paul Shen
Scaling and Charact rizing Database Workloads: Bridging the Gap between Research and Practice. MICRO (2003)
Murali Annavaram, Trung A. Diep, John Paul Shen
Branch Behavior of a Commercial OLTP Workload on Intel IA32 Processors. ICCD (2002)
Ryan N. Rakvic, Bryan Black, Deepak Limaye, John Paul Shen
Non-Vital Loads. HPCA (2002)
R. David Weldon, Steven S. Chang, Hong Wang, Gerolf Hoflehner, Perry H. Wang, Daniel M. Lavery, John Paul Shen
Quantitative Evaluation of the Register Stack Engine and Optimizations for Future Itanium Processors. Interaction between Compilers and Computer Architectures (2002)
Shih-Wei Liao, Perry H. Wang, Hong Wang, John Paul Shen, Gerolf Hoflehner, Daniel M. Lavery
Post-Pass Binary Adaptation for Software-Based Speculative Precomputation. PLDI (2002)
Perry H. Wang, Hong Wang, Jamison D. Collins, Ed Grochowski, Ralph-Michael Kling, John Paul Shen
Memory Latency-Tolerance Approaches for Itanium Processors: Out-of-Order Execution vs. Speculative Precomputation. HPCA (2002)
Perry H. Wang, Hong Wang, Ralph-Michael Kling, Kalpana Ramakrishnan, John Paul Shen
Register Renaming and Scheduling for Dynamic Execution of Predicated Code. HPCA (2001)
Jamison D. Collins, Hong Wang, Dean M. Tullsen, Christopher J. Hughes, Yong-Fong Lee, Daniel M. Lavery, John Paul Shen
Speculative precomputation: long-range prefetching of delinquent loads. ISCA (2001)
Ronny Ronen, Avi Mendelson, Konrad Lai, Shih-Lien Lu, Fred J. Pollack, John Paul Shen
Coming challenges in microarchitecture and architecture. Proc. IEEE 89 (3) (2001)
Noppanunt Utamaphethai, Ronald D. Blanton, John Paul Shen
Relating buffer-oriented microarchitecture validation to high-level pipeline functionality. HLDVT (2001)
John Paul Shen
Clear and Present Tensions in Microprocessor Design. ICCD (2001)
Deepak Limaye, Ryan N. Rakvic, John Paul Shen
Parallel Cachelets. ICCD (2001)
Jamison D. Collins, Dean M. Tullsen, Hong Wang, John Paul Shen
Dynamic speculative precomputation. MICRO (2001)
Noppanunt Utamaphethai, R. D. (Shawn) Blanton, John Paul Shen
A Buffer-Oriented Methodology for Microarchitecture Validation. J. Electron. Test. 16 (1-2) (2000)
Yuan C. Chou, Pazhani Pillai, Herman Schmit, John Paul Shen
PipeRench implementation of the instruction path coprocessor. MICRO (2000)
Noppanunt Utamaphethai, R. D. (Shawn) Blanton, John Paul Shen
Effectiveness of Microarchitecture Test Program Generation. IEEE Des. Test Comput. 17 (4) (2000)
Yuan C. Chou, John Paul Shen
Instruction path coprocessors. ISCA (2000)
Ryan N. Rakvic, Bryan Black, John Paul Shen
Completion time multiple branch prediction for enhancing trace cache performance. ISCA (2000)
Candice Bechem, Jonathan Combs, Noppanunt Utamaphethai, Bryan Black, R. D. (Shawn) Blanton, John Paul Shen
An integrated functional performance simulator. IEEE Micro 19 (3) (1999)
Yuan C. Chou, Jason Fung, John Paul Shen
Reducing branch misprediction penalties via dynamic control independence detection. International Conference on Supercomputing (1999)
Noppanunt Utamaphethai, R. D. (Shawn) Blanton, John Paul Shen
Superscalar Processor Validation at the Microarchitecture Level. VLSI Design (1999)
Bryan Black, Bohuslav Rychlik, John Paul Shen
The Block-Based Trace Cache. ISCA (1999)
Jonathan Combs, Candice Bechem Combs, John Paul Shen
Mispredicted Path Cache Effects. Euro-Par (1999)
Alexander G. Dean, John Paul Shen
System-Level Issues for Software Thread Integration: Guest Triggering and Host Selection. RTSS (1999)
Bryan Black, John Paul Shen
Calibration of Microprocessor Performance Models. Computer 31 (5) (1998)
Mikko H. Lipasti, John Paul Shen
Exploiting Value Locality to Exceed the Dataflow Limit. Int. J. Parallel Program. 26 (4) (1998)
Bryan Black, Brian Mueller, Stephanie Postal, Ryan N. Rakvic, Noppanunt Utamaphethai, John Paul Shen
Load Execution Latency Reduction. International Conference on Supercomputing (1998)
Alexander G. Dean, John Paul Shen
Techniques for Software Thread Integration in Real-Time Embedded Systems. RTSS (1998)
Alexander G. Dean, John Paul Shen
Hardware to Software Migration with Real-Time Thread Integration. EUROMICRO (1998)
Bohuslav Rychlik, John Faistl, Bryon Krug, John Paul Shen
Efficacy and Performance Impact of Value Prediction. IEEE PACT (1998)
Mikko H. Lipasti, John Paul Shen
Superspeculative Microarchitecture for Beyond AD 2000. Computer 30 (9) (1997)
Chris J. Newburn, John Paul Shen
Post-pass partitioning of signal processing programs. Int. J. Parallel Program. 25 (4) (1997)
Derek B. Noonburg, John Paul Shen
A Framework for Statistical Modeling of Superscalar Processor Performance. HPCA (1997)
Mikko H. Lipasti, John Paul Shen
The Performance Potential of Value and Dependence Prediction. Euro-Par (1997)
Yuan C. Chou, Daniel P. Siewiorek, John Paul Shen
A Realistic Study on Multithreaded Superscalar Processor Design. Euro-Par (1997)
Chris J. Newburn, John Paul Shen
Compiler Support for Low-Cost Synchronization Among Threads. PARCO (1997)
Chris J. Newburn, John Paul Shen
Automatic partitioning of signal processing programs for symmetric multiprocessors. IEEE PACT (1996)
Bryan Black, Andrew S. Huang, Mikko H. Lipasti, John Paul Shen
Can Trace-Driven Simulators Accurately Predict Superscalar Performance? ICCD (1996)
Mikko H. Lipasti, John Paul Shen
Exceeding the Dataflow Limit via Value Prediction. MICRO (1996)
Andrew S. Huang, John Paul Shen
The Intrinsic Bandwidth Requirements of Ordinary Programs. ASPLOS (1996)
Mikko H. Lipasti, Christopher B. Wilkerson, John Paul Shen
Value Locality and Load Value Prediction. ASPLOS (1996)
Andrew S. Huang, John Paul Shen
A limit study of local memory requirements using value reuse profiles. MICRO (1995)
Trung A. Diep, John Paul Shen
VMW: A Visualization-Based Microarchitecture Workbench. Computer 28 (12) (1995)
Trung A. Diep, John Paul Shen
Systematic Validation of Pipeline Interlock for Superscalar Microarchitectures. FTCS (1995)
Trung A. Diep, Christopher Nelson, John Paul Shen
Performance Evaluation of the PowerPC 620 Microarchitecture. ISCA (1995)
Derek B. Noonburg, John Paul Shen
Theoretical modeling of superscalar processor performance. MICRO (1994)
Chris J. Newburn, Derek B. Noonburg, John Paul Shen
A PDG-based Tool and its Use in Analyzing Program Control Dependences. IFIP PACT (1994)
Michael A. Schuette, John Paul Shen
Exploiting Instruction-Level Parallelism for Integrated Control-Flow Monitoring. IEEE Trans. Computers 43 (2) (1994)
Andrew S. Huang, Gert Slavenburg, John Paul Shen
Speculative Disambiguation: A Compilation Technique for Dynamic Memory Disambiguation. ISCA (1994)
Trung A. Diep, John Paul Shen, Mike Phillip
EXPLORER: a retargetable and visualization-based trace-driven simulator for superscalar processors. MICRO (1993)
Trung A. Diep, Mikko H. Lipasti, John Paul Shen
Architecture-Compatible Code Boosting for Performance Enhancement of the IBM RS/6000. ICCD (1993)
Chris J. Newburn, Andrew S. Huang, John Paul Shen
Balancing Fine- and Medium-Grained Parallelism in Scheduling Loops for the XIMD Architecture. Architectures and Compilation Techniques for Fine and Medium Grain Parallelism (1993)
Michael A. Schuette, John Paul Shen
Instruction-level experimental evaluation of the Multiflow TRACE 14/300 VLIW computer. J. Supercomput. 7 (1-2) (1993)
Scott H. Robinson, John Paul Shen
Direct Methods for Synthesis of Self-Monitoring State Machines. FTCS (1992)
Maurício Breternitz Jr., John Paul Shen
Implementation Optimization Techniques for Architecture Synthesis of Application-Specific Processors. MICRO (1991)
Michael A. Schuette, John Paul Shen
Exploiting Instruction-Level Resource Parallelism for Transparent, Integrated Control-Flow Monitoring. FTCS (1991)
Andrew Wolfe, John Paul Shen
A Variable Instruction Stream Extension to the VLIW Architecture. ASPLOS (1991)

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Publication Activity (10 Years)

Top Topics

Top Venues

John Paul Shen