Konrad Lai

Publication Activity (10 Years)

Years Active: 1988-2016
Publications (10 Years): 1

Top Topics

Top Venues

ICS 25th Anniversary

Publications

Yoongu Kim, Ross Daly, Jeremie S. Kim, Chris Fallin, Ji-Hye Lee, Donghyuk Lee, Chris Wilkerson, Konrad Lai, Onur Mutlu
RowHammer: Reliability Analysis and Security Implications. CoRR (2016)
Jih-Kwon Peir, Shih-Chang Kevin Lai, Shih-Lien Lu, Jared Stark, Konrad Lai
Author retrospective for bloom filtering cache misses for accurate data speculation and prefetching. ICS 25th Anniversary (2014)
Yoongu Kim, Ross Daly, Jeremie S. Kim, Chris Fallin, Ji-Hye Lee, Donghyuk Lee, Chris Wilkerson, Konrad Lai, Onur Mutlu
Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors. ISCA (2014)
Tomas Karnagel, Roman Dementiev, Ravi Rajwar, Konrad Lai, Thomas Legler, Benjamin Schlegel, Wolfgang Lehner
Transactional Synchronization Extensions. HPCA (2014)
Richard M. Yoo, Christopher J. Hughes, Konrad Lai, Ravi Rajwar
Performance evaluation of Intel® transactional synchronization extensions for high-performance computing. SC (2013)
Amit Gandhi, Haitham Akkary, Ravi Rajwar, Srikanth T. Srinivasan, Konrad Lai
Scalable Load and Store Processing in Latency-Tolerant Processors. IEEE Micro 26 (1) (2006)
Dinesh Somasekhar, Shih-Lien Lu, Bradley A. Bloechel, Greg Dermer, Konrad Lai, Sjeljar Borkar, Vivek De
A 10Mbit, 15GBytes/sec bandwidth 1T DRAM chip with planar MOS storage capacitor in an unmodified 150nm logic process for high-density on-chip memory applications. ESSCIRC (2005)
Lu Peng, Jih-Kwon Peir, Konrad Lai
Signature Buffer: Bridging Performance Gap between Registers and Caches. HPCA (2004)
Ayose Falcón, Jared Stark, Alex Ramírez, Konrad Lai, Mateo Valero
Prophet/Critic Hybrid Branch Prediction. ISCA (2004)
Lu Peng, Jih-Kwon Peir, Konrad Lai
A New Address-Free Memory Hierarchy Layer for Zero-Cycle Load. J. Instr. Level Parallelism 6 (2004)
Srikanth T. Srinivasan, Haitham Akkary, Tom Holman, Konrad Lai
A Minimal Dual-Core Speculative Multi-Threading Architecture. ICCD (2004)
Haitham Akkary, Srikanth T. Srinivasan, Konrad Lai
Recycling waste: exploiting wrong-path execution to improve branch prediction. ICS (2003)
Lu Peng, Jih-Kwon Peir, Qianrong Ma, Konrad Lai
Address-free memory access based on program syntax correlation of loads and stores. IEEE Trans. Very Large Scale Integr. Syst. 11 (3) (2003)
Shih-Lien Lu, Konrad Lai
Implementation of HW$im - A Real-Time Configurable Cache Simulator. FPL (2003)
Steven Hsu, Shih-Lien Lu, Shih-Chang Lai, Ram Krishnamurthy, Konrad Lai
Dynamic addressing memory arrays with physical locality. MICRO (2002)
Jih-Kwon Peir, Shih-Chang Lai, Shih-Lien Lu, Jared Stark, Konrad Lai
Bloom filtering cache misses for accurate data speculation and prefetching. ICS (2002)
Ronny Ronen, Avi Mendelson, Konrad Lai, Shih-Lien Lu, Fred J. Pollack, John Paul Shen
Coming challenges in microarchitecture and architecture. Proc. IEEE 89 (3) (2001)
Qianrong Ma, Jih-Kwon Peir, Lu Peng, Konrad Lai
Symbolic Cache: Fast Memory Access Based on Program Syntax Correlation of Loads and Stores. ICCD (2001)
Byung-Kwon Chung, Jinsuo Zhang, Jih-Kwon Peir, Shih-Chang Lai, Konrad Lai
Direct load: dependence-linked dataflow resolution of load address and cache coordinate. MICRO (2001)
Wen-Hann Wang, Jim Quinlan, Konrad Lai
Revisit the case for direct-mapped chaches: a case for two-way set-associative level-two caches. ISCA (1992)
Fred J. Pollack, Dave Johnson, Dave Carson, Ron Ebersole, Vittal Kini, Konrad Lai, Bernie Silvernail, Steve Stacey
A VLSI-intensive fault-tolerant computer architecture. Compcon (1990)
Glenn Hinton, Konrad Lai, Randy Steck
Microarchitecture of the 80960 high-integration processors. ICCD (1988)