Paul Chow

ORCID

Publication Activity (10 Years)

Years Active: 1983-2024
Publications (10 Years): 53

Top Venues

Publications

Mohammad Ewais, Paul Chow
DDC: A Vision for a Disaggregated Datacenter. CoRR (2024)
Paul Chow
The Software-Centric Approach of SYNERGY: Technical Perspective. Commun. ACM 67 (8) (2024)
Yu Gao, Juan Camilo Vega, Paul Chow
The Feasibility of Implementing Large-Scale Transformers on Multi-FPGA Platforms. CoRR (2024)
Qianfeng Shen, Paul Chow
A Lightweight Routing Layer Using a Reliable Link-Layer Protocol. CoRR (2023)
Mohammad Ewais, Paul Chow
Disaggregated Memory in the Datacenter: A Survey. IEEE Access 11 (2023)
Qianfeng Shen, Jun Zheng, Paul Chow
RIFL: A Reliable Link Layer Network Protocol for Data Center Communication. CoRR (2023)
Qiangfeng Shen, Paul Chow
A Lightweight Routing Layer Using a Reliable Link-Layer Protocol. CloudCom (2023)
Mohammadmahdi Mazraeli, Yu Gao, Paul Chow
Partitioning Large-Scale, Multi-FPGA Applications for the Data Center. FPL (2023)
Naif Tarafdar, Giuseppe Di Guglielmo, Philip C. Harris, Jeffrey D. Krupa, Vladimir Loncar, Dylan S. Rankin, Nhan Tran, Zhenbin Wu, Qianfeng Shen, Paul Chow
: An Open Framework for Deploying Machine Learning on Heterogeneous Clusters. ACM Trans. Reconfigurable Technol. Syst. 15 (3) (2022)
Christophe Bobda, Joel Mandebi Mbongue, Paul Chow, Mohammad Ewais, Naif Tarafdar, Juan Camilo Vega, Ken Eguro, Dirk Koch, Suranga Handagala, Miriam Leeser, Martin C. Herbordt, Hafsah Shahzad, Peter Hofste, Burkhard Ringlein, Jakub Szefer, Ahmed Sanaullah, Russell Tessier
The Future of FPGA Acceleration in Datacenters and the Cloud. ACM Trans. Reconfigurable Technol. Syst. 15 (3) (2022)
Qianfeng Clark Shen, Juan Camilo Vega, Paul Chow
Parallel CRC On An FPGA At Terabit Speeds. FPT (2022)
Qianfeng Shen, Jun Zheng, Paul Chow
RIFL: a reliable link layer network protocol for data center communication. JOCN 14 (3) (2022)
Arzhang Rafii, Welson Sun, Paul Chow
Pharos: a Multi-FPGA Performance Monitor. FPL (2021)
Varun Sharma, Paul Chow
Exploring PGAS Communication for Heterogeneous Clusters with FPGAs. FPGA (2021)
Mohammad Ewais, Juan Camilo Vega, Alberto Leon-Garcia, Paul Chow
A Framework Integrating FPGAs in VNF Networks. NoF (2021)
Jun Li, Paul Chow, Yuanxi Peng, Tian Jiang
FPGA Implementation of an Improved OMP for Compressive Sensing Reconstruction. IEEE Trans. Very Large Scale Integr. Syst. 29 (2) (2021)
Qianfeng Clark Shen, Jun Zheng, Paul Chow
RIFL: A Reliable Link Layer Network Protocol for FPGA-to-FPGA Communication. FPGA (2021)
Marco Antonio Merlini, Isamu Poy, Paul Chow
Interactive Debugging at IP Block Interfaces in FPGAs. FPGA (2021)
Arzhang Rafii, Paul Chow, Welson Sun
Pharos: a Performance Monitor for Multi-FPGA Systems. FCCM (2021)
Varun Sharma, Paul Chow
A PGAS Communication Library for Heterogeneous Clusters. CoRR (2021)
Juan Camilo Vega, Mohammad Ewais, Alberto Leon-Garcia, Paul Chow
FFIVE: An FPGA Framework for Interactive VNF Environments. FCCM (2021)
Juan Camilo Vega, Qianfeng Clark Shen, Paul Chow
SHIP: Storage for Hybrid Interconnected Processors. FCCM (2020)
Juan Camilo Vega, Marco Antonio Merlini, Paul Chow
FFShark: A 100G FPGA Implementation of BPF Filtering for Wireshark. FCCM (2020)
Charles Lo, Paul Chow
Hierarchical Modelling of Generators in Design-Space Exploration. FCCM (2020)
Naif Tarafdar, Giuseppe Di Guglielmo, Philip C. Harris, Jeffrey D. Krupa, Vladimir Loncar, Dylan S. Rankin, Nhan Tran, Zhenbin Wu, Qianfeng Shen, Paul Chow
AIgean: An Open Framework for Machine Learning on Heterogeneous Clusters. FCCM (2020)
Nariman Eskandari, Naif Tarafdar, Daniel Ly-Ma, Paul Chow
A Modular Heterogeneous Stack for Deploying FPGAs and CPUs in the Data Center. FPGA (2019)
Daniel Rozhko, Paul Chow
The Network Management Unit (NMU): Securing Network Access for Direct-Connected FPGAs. FPGA (2019)
Varun Sharma, Naif Tarafdar, Paul Chow
Sonar: Writing Testbenches through Python. FCCM (2019)
Ehsan Ghasemi, Paul Chow
Accelerating Apache Spark with FPGAs. Concurr. Comput. Pract. Exp. 31 (2) (2019)
Juan Camilo Vega, Qianfeng Shen, Alberto Leon-Garcia, Paul Chow
Introducing ReCPRI: A Field Re-configurable Protocol for Backhaul Communication in a Radio Access Network. IM (2019)
Abdul-Amir Yassine, Yasmin Afsharnejad, Omar Ragheb, Vaughn Betz, Paul Chow
A High-Level Synthesis Case Study on Light Propagation Simulation in Turbid Media. FCCM (2018)
Naif Tarafdar, Nariman Eskandari, Thomas Lin, Paul Chow
Designing for FPGAs in the Cloud. IEEE Des. Test 35 (1) (2018)
Yasmin Afsharnejad, Abdul-Amir Yassine, Omar Ragheb, Paul Chow, Vaughn Betz
HLS-based FPGA Acceleration of Light Propagation Simulation in Turbid Media. HEART (2018)
Charles Lo, Paul Chow
Multi-fidelity Optimization for High-Level Synthesis Directives. FPL (2018)
Naif Tarafdar, Nariman Eskandari, Varun Sharma, Charles Lo, Paul Chow
Galapagos: A Full Stack Approach to FPGA Integration in the Cloud. IEEE Micro 38 (6) (2018)
Naif Tarafdar, Thomas Lin, Eric Fukuda, Hadi Bannazadeh, Alberto Leon-Garcia, Paul Chow
Enabling Flexible Network FPGA Clusters in a Heterogeneous Cloud Data Center. FPGA (2017)
Naif Tarafdar, Thomas Lin, Nariman Eskandari, David Lion, Alberto Leon-Garcia, Paul Chow
Heterogeneous virtualized network function framework for the data center. FPL (2017)
Daniel Rozhko, Geoffrey Elliott, Daniel Ly-Ma, Paul Chow, Hans-Arno Jacobsen
Packet Matching on FPGAs Using HMC Memory: Towards One Million Rules. FPGA (2017)
Vincent Mirian, Paul Chow
Enabling FPGAs as a True Device in the OpenCL Standard: Bridging the Gap for FPGAs. IWOCL (2017)
Paul Chow
Building the Reconfigurable Cloud Ecosystem. ETCD@ASPLOS (2017)
Thomas Lin, Naif Tarafdar, Byungchul Park, Paul Chow, Alberto Leon-Garcia
Enabling network function virtualization over heterogeneous resources. APNOMS (2017)
Andrew Boutros, Brett Grady, Mustafa Abbas, Paul Chow
Build fast, trade fast: FPGA-based high-frequency trading using high-level synthesis. ReConFig (2017)
Roberto DiCecco, Lin Sun, Paul Chow
FPGA-based training of convolutional neural networks with a reduced precision floating-point library. FPT (2017)
Fernando Martin del Campo, Paul Chow
Task replication and control for highly parallel in-memory stores. MEMSYS (2017)
Zhiqiang Liu, Yong Dou, Jingfei Jiang, Qiang Wang, Paul Chow
An FPGA-based processor for training convolutional neural networks. FPT (2017)
Roberto DiCecco, Griffin Lacey, Jasmina Vasiljevic, Paul Chow, Graham W. Taylor, Shawki Areibi
Caffeinated FPGAs: FPGA Framework For Convolutional Neural Networks. CoRR (2016)
Roberto DiCecco, Griffin Lacey, Jasmina Vasiljevic, Paul Chow, Graham W. Taylor, Shawki Areibi
Caffeinated FPGAs: FPGA framework For Convolutional Neural Networks. FPT (2016)
Charles Lo, Paul Chow
Model-based optimization of High Level Synthesis directives. FPL (2016)
Jianfeng Zhang, Paul Chow, Hengzhu Liu
CORDIC-Based Enhanced Systolic Array Architecture for QR Decomposition. ACM Trans. Reconfigurable Technol. Syst. 9 (2) (2016)
Ehsan Ghasemi, Paul Chow
Accelerating Apache Spark Big Data Analysis with FPGAs. UIC/ATC/ScalCom/CBDCom/IoP/SmartWorld (2016)
Vincent Mirian, Paul Chow
Extracting Designs of Secure IPs Using FPGA CAD Tools. ACM Great Lakes Symposium on VLSI (2016)
Ehsan Ghasemi, Paul Chow
A Scalable Heterogeneous Dataflow Architecture For Big Data Analytics Using FPGAs (Abstract Only). FPGA (2016)
Ehsan Ghasemi, Paul Chow
Accelerating Apache Spark Big Data Analysis with FPGAs. FCCM (2016)
Jasmina Vasiljevic, Ralph Wittig, Paul Schumacher, Jeff Fifield, Fernando Martinez-Vallina, Henry Styles, Paul Chow
OpenCL library of stream memory components targeting FPGAs. FPT (2015)
Jianfeng Zhang, Paul Chow, Hengzhu Liu
An Enhanced Adaptive Recoding Rotation CORDIC. ACM Trans. Reconfigurable Technol. Syst. 9 (1) (2015)
Stuart Byma, Naif Tarafdar, Talia Xu, Hadi Bannazadeh, Alberto Leon-Garcia, Paul Chow
Expanding OpenFlow Capabilities with Virtualized Reconfigurable Hardware. FPGA (2015)
Jianfeng Zhang, Paul Chow, Hengzhu Liu
FPGA implementation of low-power and high-PSNR DCT/IDCT architecture based on adaptive recoding CORDIC. FPT (2015)
Vincent Mirian, Paul Chow
Exploring pipe implementations using an OpenCL framework for FPGAs. FPT (2015)
Vincent Mirian, Paul Chow
Evaluating shared virtual memory in an OpenCL framework for embedded systems on FPGAs. ReConFig (2015)
Vincent Mirian, Paul Chow
UT-OCL: an OpenCL framework for embedded systems using xilinx FPGAs. ReConFig (2015)
Fernando Martin del Campo, Paul Chow
Architecture Exploration for Data Intensive Applications. MEMSYS (2015)
Jasmina Vasiljevic, Paul Chow
MPack: global memory optimization for stream applications in high-level synthesis. FPGA (2014)
Stuart Byma, Hadi Bannazadeh, Alberto Leon-Garcia, J. Gregory Steffan, Paul Chow
Virtualized Reconfigurable Hardware Resources in the SAVI Testbed. TRIDENTCOM (2014)
Ruediger Willenberg, Paul Chow
A Software Parallel Programming Approach to FPGA-Accelerated Computing. CoRR (2014)
Stuart Byma, J. Gregory Steffan, Hadi Bannazadeh, Alberto Leon-Garcia, Paul Chow
FPGAs in the Cloud: Booting Virtualized Hardware Accelerators with OpenStack. FCCM (2014)
Vincent Mirian, Paul Chow
Using an OpenCL framework to evaluate interconnect implementations on FPGAs. FPL (2014)
Yuan Li, Paul Chow, Jiang Jiang, Minxuan Zhang, Shaojun Wei
Software/Hardware Parallel Long-Period Random Number Generation Framework Based on the WELL Method. IEEE Trans. Very Large Scale Integr. Syst. 22 (5) (2014)
Yuanxi Peng, Manuel Saldaña, Christopher A. Madill, Xiaofeng Zou, Paul Chow
Benefits of Adding Hardware Support for Broadcast and Reduce Operations in MPSoC Applications. ACM Trans. Reconfigurable Technol. Syst. 7 (3) (2014)
Ruediger Willenberg, Paul Chow
A Heterogeneous GASNet Implementation for FPGA-accelerated Computing. PGAS (2014)
Jianfeng Zhang, Paul Chow, Hengzhu Liu
An efficient FPGA implementation of QR decomposition using a novel systolic array architecture based on enhanced vectoring CORDIC. FPT (2014)
Jasmina Vasiljevic, Paul Chow
Using buffer-to-BRAM mapping approaches to trade-off throughput vs. memory use. FPL (2014)
Ruediger Willenberg, Paul Chow
A remote memory access infrastructure for global address space programming models in FPGAs. FPGA (2013)
Paul Chow
Why Put FPGAs in your CPU socket? FPT (2013)
Ruediger Willenberg, Paul Chow
Simulation-based HW/SW co-debugging for field-programmable systems-on-chip. FPL (2013)
Ruediger Willenberg, Paul Chow
SimXMD: Simulation-based HW/SW co-debugging. FPL (2013)
Stuart Byma, J. Gregory Steffan, Paul Chow
NetThreads-10G: Software packet processing on NetFPGA-10G in a virtualized networking environment demonstration abstract. FPL (2013)
Zhongduo Lin, Paul Chow
ZCluster: A Zynq-based Hadoop cluster. FPT (2013)
S. Alexander Chin, Paul Chow
OpenCL memory infrastructure for FPGAs (abstract only). FPGA (2012)
Vincent Mirian, Paul Chow
Managing mutex variables in a cache-coherent shared-memory system for FPGAs. FPT (2012)
Charles Lo, Paul Chow
A high-performance architecture for training Viola-Jones object detectors. FPT (2012)
Vincent Mirian, Paul Chow
FCache: a system for cache coherent processing on FPGAs. FPGA (2012)
Yuan Li, Paul Chow, Jiang Jiang, Minxuan Zhang, Shaojun Wei
Software/hardware framework for generating parallel Gaussian random numbers based on the Monty Python method. FPT (2012)
Manuel Saldaña, Arun Patel, Hao Jun Liu, Paul Chow
Using Partial Reconfiguration and Message Passing to Enable FPGA-Based Generic Computing Platforms. Int. J. Reconfigurable Comput. 2012 (2012)
Vincent Mirian, Paul Chow
An implementation of a directory protocol for a cache coherent system on FPGAs. ReConFig (2012)
Zhongduo Lin, Charles Lo, Paul Chow
K-means implementation on FPGA for high-dimensional data using triangle inequality. FPL (2012)
Ruediger Willenberg, Paul Chow
SimXMD: Integrated debugging of C code and hardware components. FPT (2012)
Yuan Li, Paul Chow, Jiang Jiang, Minxuan Zhang
Software/Hardware Framework for Generating Parallel Long-Period Random Numbers Using the WELL Method. FPL (2011)
Lesley Shannon, Paul Chow
Leveraging reconfigurability in the hardware/software codesign process. ACM Trans. Reconfigurable Technol. Syst. 4 (3) (2011)
Charles Lo, Paul Chow
Building a multi-FPGA virtualized restricted boltzmann machine architecture using embedded MPI. FPGA (2011)
Yuanxi Peng, Manuel Saldaña, Paul Chow
Hardware Support for Broadcast and Reduce in MPSoC. FPL (2011)
Alexander Kaganov, Asif Lakhany, Paul Chow
FPGA Acceleration of MultiFactor CDO Pricing. ACM Trans. Reconfigurable Technol. Syst. 4 (2) (2011)
Manuel Saldaña, Arun Patel, Hao Jun Liu, Paul Chow
Using Partial Reconfiguration in an Embedded Message-Passing System. ReConFig (2010)
Andrew W. H. House, Manuel Saldaña, Paul Chow
Integrating High-Level Synthesis into MPI. FCCM (2010)
Hadi Bannazadeh, Alberto Leon-Garcia, Keith Redmond, Gordon Tam, Arbab Khan, Mingliang Ma, Saleh Dani, Paul Chow
Virtualized Application Networking Infrastructure. TRIDENTCOM (2010)
Dharmendra P. Gupta, Paul Chow
Acceleration of an analytical approach to collateralized debt obligation pricing. FPGA (2010)
Daniel Le Ly, Paul Chow
High-Performance Reconfigurable Hardware Architecture for Restricted Boltzmann Machines. IEEE Trans. Neural Networks 21 (11) (2010)
Manuel Saldaña, Arun Patel, Christopher A. Madill, Daniel Nunes, Danyao Wang, Paul Chow, Ralph Wittig, Henry Styles, Andrew Putnam
MPI as a Programming Model for High-Performance Reconfigurable Computers. ACM Trans. Reconfigurable Technol. Syst. 3 (4) (2010)
Paul Chow, Manuel Saldaña, Arun Patel, Christopher A. Madill
Programming the Nallatech Xeon + multi-FPGA heterogeneous platform. Hot Chips Symposium (2009)
Daniel Le Ly, Paul Chow
A high-performance FPGA architecture for restricted boltzmann machines. FPGA (2009)
Jiang Jiang, Vincent Mirian, Kam Pui Tang, Paul Chow, Zuocheng Xing
Matrix Multiplication Based on Scalable Macro-Pipelined FPGA Accelerator Architecture. ReConFig (2009)

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Publication Activity (10 Years)

Top Topics

Top Venues

Paul Chow