Zuocheng Xing

Publication Activity (10 Years)

Years Active: 2006-2022
Publications (10 Years): 29

Top Topics

Hardware Architecture

Qr Decomposition

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Zerun Li, Qinglin Wang, Yufei Zhu, Zuocheng Xing
Automatic Modulation Classification for MASK, MPSK, and MQAM Signals Based on Hierarchical Self-Organizing Map. Sensors 22 (17) (2022)
Xing Hu, Yang Zhang, Li Mao, Jie Shen, Zuocheng Xing
A Noc Centric Low Overhead Multi-chip Interconnection Technology. HPCC/DSS/SmartCity/DependSys (2021)
Yufei Zhu, Zuocheng Xing, Jinhui Xue, Zerun Li, Yifan Hu, Yang Zhang, Yongzhong Li
Area-Efficient Parallel Reconfigurable Stream Processor for Symmetric Cryptograph. IEEE Access 9 (2021)
Yufei Zhu, Zuocheng Xing, Zerun Li, Yang Zhang, Yifan Hu
High Area-Efficient Parallel Encoder with Compatible Architecture for 5G LDPC Codes. Symmetry 13 (4) (2021)
Lirui Chen, Yu Wang, Zuocheng Xing, Shikai Qiu, Qinglin Wang, Yongzhong Li
Low latency group-sorted QR decomposition algorithm for larger-scale MIMO systems. IET Commun. 15 (12) (2021)
Zerun Li, Qinglin Wang, Weisong Liu, Qiang Xu, Zuocheng Xing, Yongzhong Li
Practical AMC model based on SAE with various optimisation methods under different noise environments. IET Commun. 14 (22) (2020)
Lirui Chen, Yu Wang, Zuocheng Xing, Shikai Qiu, Qinglin Wang, Yang Zhang
A Paralleled Greedy LLL Algorithm for 16×16 MIMO Detection. ISCAS (2020)
Lirui Chen, Zuocheng Xing, Yongzhong Li, Shikai Qiu
Efficient MIMO Preprocessor With Sorting-Relaxed QR Decomposition and Modified Greedy LLL Algorithm. IEEE Access 8 (2020)
Yu Wang, Qinglin Wang, Yang Zhang, Shikai Qiu, Zuocheng Xing
An Area-Efficient Hybrid Polar Decoder With Pipelined Architecture. IEEE Access 8 (2020)
Yu Wang, Shikai Qiu, Lirui Chen, Qinglin Wang, Yang Zhang, Cang Liu, Zuocheng Xing
A Low-Latency Successive Cancellation Hybrid Decoder for Convolutional Polar Codes. ICASSP (2020)
Yu Wang, Lirui Chen, Cang Liu, Zuocheng Xing
An Improved Concatenation Scheme of BCH-Polar Codes With Low-Latency Decoding Architecture. IEEE Access 7 (2019)
Yu Wang, Lirui Chen, Qinglin Wang, Yang Zhang, Zuocheng Xing
Algorithm and Architecture for Path Metric Aided Bit-Flipping Decoding of Polar Codes. WCNC (2019)
Yang Zhang, Zuocheng Xing, Yu Wang, Lirui Chen, Qinglin Wang, Yufei Zhu
Optimization Methods for Computing System in Mobile CPS. ICBDT (2019)
Yang Zhang, Zuocheng Xing, Cang Liu, Chuan Tang
CWLP: coordinated warp scheduling and locality-protected cache allocation on GPUs. Frontiers Inf. Technol. Electron. Eng. 19 (2) (2018)
Yang Zhang, Zuocheng Xing, Chuan Tang, Cang Liu
Locality-protected cache allocation scheme with low overhead on GPUs. IET Comput. Digit. Tech. 12 (3) (2018)
Yang Zhang, Zuocheng Xing, Cang Liu, Chuan Tang, Qinglin Wang
Locality based warp scheduling in GPGPUs. Future Gener. Comput. Syst. 82 (2018)
Yu Wang, Lirui Chen, Shikai Qiu, Li Huang, Zuocheng Xing
A Low Latency SCAN-Flip Polar Decoder for 5G Vehicular Communication. INTSYS (2018)
Lirui Chen, Cang Liu, Yu Wang, Zuocheng Xing, Yang Zhang, Jing Liu
Low latency QRD algorithm for future communication. IEICE Electron. Express 14 (22) (2017)
Chuan Tang, Cang Liu, Luechao Yuan, Zuocheng Xing
Approximate iteration detection with iterative refinement in massive MIMO systems. IET Commun. 11 (7) (2017)
Luechao Yuan, Cang Liu, Chuan Tang, Shan Huang, Anupam Chattopadhyay, Gerd Ascheid, Zuocheng Xing
A Flexible Divide-and-Conquer MPSoC Architecture for MIMO Interference Cancellation. IEEE Trans. Very Large Scale Integr. Syst. 25 (10) (2017)
Cang Liu, Chuan Tang, Zuocheng Xing, Luechao Yuan, Yang Zhang
Hardware Architecture Based on Parallel Tiled QRD Algorithm for Future MIMO Systems. IEEE Trans. Very Large Scale Integr. Syst. 25 (5) (2017)
Cang Liu, Zuocheng Xing, Luechao Yuan, Chuan Tang, Yang Zhang
A Novel Architecture to Eliminate Bottlenecks in a Parallel Tiled QRD Algorithm for Future MIMO Systems. IEEE Trans. Circuits Syst. II Express Briefs (1) (2017)
Cang Liu, Chuan Tang, Zuocheng Xing, Lirui Chen, Yang Zhang, Guitao Fu
An Architecture of Parallel Tiled QRD Algorithm for MIMO-OFDM Systems. Trustcom/BigDataSE/ISPA (2016)
Cang Liu, Chuan Tang, Luechao Yuan, Zuocheng Xing, Yang Zhang
QR decomposition architecture using the iteration look-ahead modified Gram-Schmidt algorithm. IET Circuits Devices Syst. 10 (5) (2016)
Chuan Tang, Cang Liu, Luechao Yuan, Zuocheng Xing
High Precision Low Complexity Matrix Inversion Based on Newton Iteration for Data Detection in the Massive MIMO. IEEE Commun. Lett. 20 (3) (2016)
Cang Liu, Chuan Tang, Zuocheng Xing, Luechao Yuan, Yu Wang, Lirui Chen, Yang Zhang, Suncheng Xiang, Wangfeng Zhao, Xing Hu, Jinsong Xu
QRD Architecture Using the Modified ILMGS Algorithm for MIMO Systems. WICON (2016)
Yang Zhang, Zuocheng Xing, Li Zhou, Chunsheng Zhu
Locality Protected Dynamic Cache Allocation Scheme on GPUs. Trustcom/BigDataSE/ISPA (2016)
Yang Zhang, Zuocheng Xing, Cang Liu, Chuan Tang, Lirui Chen, Qinglin Wang
Optimization of Two Bottleneck Programs in SAR System on GPGPU. NCCET (2016)
Suncheng Xiang, Minxuan Zhang, Zuocheng Xing, Cang Liu
Hardware design of ML algorithm in MIMO-OFDM system. ICSAI (2016)
Luechao Yuan, Gaojiang Wang, Gerd Ascheid, Cang Liu, Zuocheng Xing
A flexible low-complexity robust THP approach for MISO downlinks with imperfect CSI. ICCC (2015)
Qinglin Wang, Jie Liu, Chunye Gong, Yang Zhang, Zuocheng Xing
A GPU-based Fast Solution for Riesz Space Fractional Reaction-Diffusion Equation. NBiS (2015)
Feng Wang, Xiantuo Tang, Zuocheng Xing
Applying Partial Power-Gating to Direction-Sliced Network-on-Chip. J. Electr. Comput. Eng. 2015 (2015)
Yang Zhang, Zuocheng Xing, Xiao Ma
DIPP - An LLC Replacement Policy for On-chip Dynamic Heterogeneous Multi-core Architecture. ICYCSEE (2015)
Feng Wang, Xiantuo Tang, Zuocheng Xing
Applying partial power-gating to bit-sliced network-on-chip. Microelectron. J. 46 (11) (2015)
Chuan Tang, Cang Liu, Luechao Yuan, Zuocheng Xing
Channel Estimation in Massive MIMO: Algorithm and Hardware. NCCET (2015)
Chuan Tang, Dan Liu, Zuocheng Xing, Peng Yang, Zhe Wang, Jiang Xu
Memory Access Analysis of Many-core System with Abundant Bandwidth. MCSoC (2015)
Cang Liu, Luechao Yuan, Zuocheng Xing, Xiantuo Tang, Guitao Fu
A ML-Based High-Accuracy Estimation of Sampling and Carrier Frequency Offsets for OFDM Systems. NCCET (2015)
Feng Wang, Xiantuo Tang, Zuocheng Xing, Hengzhu Liu
UniMESH: The light-weight unidirectional channel Network-on-Chip in 2D mesh topology. CONIELECOMP (2015)
Qinglin Wang, Jie Liu, Xiantao Cui, Guitao Fu, Chunye Gong, Zuocheng Xing
Accelerating FDTD simulation of microwave pulse coupling into narrow slots on the Intel MIC architecture. PACRIM (2015)
Feng Wang, Xiantuo Tang, Qinglin Wang, Zuocheng Xing, Hengzhu Liu
Flexible Virtual Channel Power-Gating for High-Throughput and Low-Power Network-on-Chip. DSD (2014)
Yang Zhang, Zuocheng Xing, Luechao Yuan, Cang Liu, Qinglin Wang
The acceleration of turbo decoder on the newest GPGPU of Kepler architecture. ISCIT (2014)
Qinglin Wang, Zuocheng Xing, Jie Liu, Xiaogang Qiang, Chunye Gong, Jiang Jiang
Parallel 3D deterministic particle transport on Intel MIC architecture. HPCS (2014)
Chaochao Feng, Zhonghai Lu, Axel Jantsch, Minxuan Zhang, Zuocheng Xing
Addressing Transient and Permanent Faults in NoC With Efficient Fault-Tolerant Deflection Router. IEEE Trans. Very Large Scale Integr. Syst. 21 (6) (2013)
Xiantuo Tang, Feng Wang, Zuocheng Xing, Qinglin Wang
Backhaul-Route Pre-Configuration Mechanism for Delay Optimization in NoCs. NCCET (2013)
Jun Gao, Minxuan Zhang, Zuocheng Xing, Chaochao Feng
Architecture and Implementation of a Reduced EPIC Processor. IEICE Trans. Inf. Syst. (1) (2013)
Xiaobao Chen, Zuocheng Xing, Bingcai Sui, Shi-Ce Ni
Reconfigurable pseudo-NMOS-like logic with hybrid MOS and single-electron transistors. IEICE Electron. Express 10 (20) (2013)
Xiaobao Chen, Zuocheng Xing, Bingcai Sui
A Full Adder Based on Hybrid Single-Electron Transistors and MOSFETs at Room Temperature. NCCET (2013)
Luechao Yuan, Zuocheng Xing, Yang Zhang, Xiaobao Chen
An Optimizing Strategy Research of LDPC Decoding Based on GPGPU. TrustCom/ISPA/IUCC (2013)
Xiaobao Chen, Zuocheng Xing, Bingcai Sui
Tunable Negative Differential Resistance of Single-Electron Transistor Controlled by Capacitance. NCCET (2013)
Xiaobao Chen, Zuocheng Xing, Bingcai Sui
Validation and analysis of negative differential resistance of single-electron transistor with conductance model. ICECS (2012)
Xiaobao Chen, Zuocheng Xing, Bingcai Sui
A model for energy quantization of single-electron transistor below 10nm. ASICON (2011)
Guitao Fu, Zuocheng Xing, Tianlei Zhao, Xiantuo Tang
Design and Evaluation of Traffic Filter for Token Protocol. PARELEC (2011)
Yu Cheng, Yongwen Wang, Zuocheng Xing, Minxuan Zhang
Characterizing Time-Varying Behavior and Predictability of Cache AVF. INCoS (2011)
Anguo Ma, Yu Cheng, Zuocheng Xing
Accurate and Simplified Prediction of AVF for Delay and Energy Efficient Cache Design. J. Comput. Sci. Technol. 26 (3) (2011)
Shubo Qi, Jinwen Li, Zuocheng Xing, Xiaomin Jia, Minxuan Zhang
A Delay Model of Two-Cycle NoC Router in 2D-Mesh Network. ISVLSI (2010)
Anguo Ma, Jing Cai, Yu Cheng, Xiaoqiang Ni, Yuxing Tang, Zuocheng Xing
Performance Optimization Strategies of High Performance Computing on GPU. APPT (2009)
Jiang Jiang, Vincent Mirian, Kam Pui Tang, Paul Chow, Zuocheng Xing
Matrix Multiplication Based on Scalable Macro-Pipelined FPGA Accelerator Architecture. ReConFig (2009)
Ping Zhang, Yanmin Song, Jianmin Zhang, Zuocheng Xing
Design of Testing Struture in Microprocessor Based on JTAG. ISCID (1) (2009)
Xuejun Yang, Xiaobo Yan, Zuocheng Xing, Yu Deng, Jiang Jiang, Jing Du, Ying Zhang
Fei Teng 64 Stream Processing System: Architecture, Compiler, and Programming. IEEE Trans. Parallel Distributed Syst. 20 (8) (2009)
Xuejun Yang, Xiaobo Yan, Zuocheng Xing, Yu Deng, Jiang Jiang, Ying Zhang
A 64-bit stream processor architecture for scientific applications. ISCA (2007)
Chengyi Zhang, Hongwei Zhou, Minxuan Zhang, Zuocheng Xing
An Architectural Leakage Power Reduction Method for Instruction Cache in Ultra Deep Submicron Microprocessors. Asia-Pacific Computer Systems Architecture Conference (2006)