Matrix Multiplication Based on Scalable Macro-Pipelined FPGA Accelerator Architecture.
Jiang JiangVincent MirianKam Pui TangPaul ChowZuocheng XingPublished in: ReConFig (2009)
Keyphrases
- matrix multiplication
- parallel architecture
- field programmable gate array
- distributed memory
- hardware implementation
- data flow
- hardware design
- hardware architecture
- parallel implementation
- real time
- fpga technology
- fpga implementation
- software implementation
- systolic array
- pipelined architecture
- multi processor
- fpga device
- hardware architectures
- message passing
- xilinx virtex
- software architecture
- shared memory
- dedicated hardware
- high speed
- image processing
- parallel computing
- processing elements
- highly efficient
- reconfigurable hardware