An Architectural Leakage Power Reduction Method for Instruction Cache in Ultra Deep Submicron Microprocessors.
Chengyi ZhangHongwei ZhouMinxuan ZhangZuocheng XingPublished in: Asia-Pacific Computer Systems Architecture Conference (2006)
Keyphrases
- reduction method
- instruction set
- memory subsystem
- memory hierarchy
- computing power
- computer architecture
- selection algorithm
- cache misses
- power consumption
- floating point
- level parallelism
- high speed
- low power
- prefetching
- multithreading
- vlsi circuits
- single chip
- database
- main memory
- memory access
- query processing
- search algorithm
- multiscale
- nearest neighbor
- data structure
- training data