Architecture and Implementation of a Reduced EPIC Processor.
Jun GaoMinxuan ZhangZuocheng XingChaochao FengPublished in: IEICE Trans. Inf. Syst. (2013)
Keyphrases
- instruction set
- parallel architecture
- layered architecture
- computation intensive
- single instruction multiple data
- memory management
- multi processor
- hardware implementation
- architectural design
- industry standard
- design considerations
- hardware architecture
- hardware architectures
- vlsi architecture
- vlsi implementation
- software implementation
- platform independent
- hardware design
- floating point
- design methodology
- high speed
- neural network
- data flow
- xilinx virtex
- parallel processing
- processing elements
- network architecture
- embedded systems
- fpga device
- software architecture
- java platform