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An efficient FPGA implementation of QR decomposition using a novel systolic array architecture based on enhanced vectoring CORDIC.
Jianfeng Zhang
Paul Chow
Hengzhu Liu
Published in:
FPT (2014)
Keyphrases
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fpga implementation
systolic array
hardware implementation
parallel architecture
reconfigurable architecture
qr decomposition
data flow
field programmable gate array
image processing algorithms
signal processing
real time
data sets
neural network
low cost