Chenlei Fang

Publication Activity (10 Years)

Years Active: 2014-2023
Publications (10 Years): 15

Top Topics

Nearest Neighbor

Sparse Approximation

Reduction Method

Top Venues

Publications

Chenlei Fang, Qicheng Huang, Zeye Liu, Ruizhou Ding, Ronald D. Blanton
Efficient Test Chip Design via Smart Computation. ACM Trans. Design Autom. Electr. Syst. 28 (2) (2023)
Chenlei Fang, Qicheng Huang, R. D. Shawn Blanton
Memory-Efficient Adaptive Test Pattern Reordering for Accurate Diagnosis. VTS (2021)
Qicheng Huang, Chenlei Fang, Soumya Mittal, R. D. (Shawn) Blanton
Towards Smarter Diagnosis: A Learning-based Diagnostic Outcome Previewer. ACM Trans. Design Autom. Electr. Syst. 25 (5) (2020)
Chenlei Fang, Qicheng Huang, R. D. Shawn Blanton
Adaptive Test Pattern Reordering for Diagnosis using k-Nearest Neighbors. ITC-Asia (2020)
Qicheng Huang, Chenlei Fang, R. D. Shawn Blanton
Diagnosis Outcome Prediction on Limited Data via Transferred Random Forest. ITC-Asia (2020)
Qicheng Huang, Chenlei Fang, R. D. Shawn Blanton
LAIDAR: Learning for Accuracy and Ideal Diagnostic Resolution. ITC (2020)
Qicheng Huang, Chenlei Fang, R. D. Shawn Blanton
Knowledge Transfer for Diagnosis Outcome Preview with Limited Data. ITC (2020)
Chenlei Fang, Qicheng Huang, Soumya Mittal, R. D. Shawn Blanton
Diagnosis Outcome Preview through Learning. VTS (2019)
Zeye Liu, Qicheng Huang, Chenlei Fang, R. D. (Shawn) Blanton
Improving Test Chip Design Efficiency via Machine Learning. ITC (2019)
Qicheng Huang, Chenlei Fang, Zeye Liu, Ruizhou Ding, R. D. Shawn Blanton
IPSA: Integer Programming via Sparse Approximation for Efficient Test-Chip Design. ICCD (2019)
Qicheng Huang, Chenlei Fang, Soumya Mittal, R. D. Shawn Blanton
Improving Diagnosis Efficiency via Machine Learning. ITC (2018)
Chenlei Fang, Qicheng Huang, Fan Yang, Xuan Zeng, Dian Zhou, Xin Li
Efficient performance modeling of analog integrated circuits via kernel density based sparse regression. DAC (2016)
Qicheng Huang, Xiao Li, Chenlei Fang, Fan Yang, Yangfeng Su, Xuan Zeng
An aggregating based model order reduction method for power grids. Integr. 55 (2016)
Qicheng Huang, Chenlei Fang, Fan Yang, Xuan Zeng, Dian Zhou, Xin Li
Efficient performance modeling via Dual-Prior Bayesian Model Fusion for analog and mixed-signal circuits. DAC (2016)
Xuan Zeng, Chenlei Fang, Qicheng Huang, Fan Yang, Dian Zhou, Wei Cai, Weiping Shi
High-speed link verification based on statistical inference. ISCAS (2016)
Chenlei Fang, Qicheng Huang, Fan Yang, Xuan Zeng, Xin Li, Chenjie Gu
Efficient bit error rate estimation for high-speed link by Bayesian model fusion. DATE (2015)
Qicheng Huang, Xiao Li, Chenlei Fang, Fan Yang, Yangfeng Su, Xuan Zeng
PGMOR: An Efficient Model Order Reduction Method for Power Grids. CAD/Graphics (2015)
Qicheng Huang, Chenlei Fang, Fan Yang, Xuan Zeng, Xin Li
Efficient multivariate moment estimation via Bayesian model fusion for analog and mixed-signal circuits. DAC (2015)
Chenlei Fang, Fan Yang, Xuan Zeng, Xin Li
BMF-BD: Bayesian Model Fusion on Bernoulli Distribution for Efficient Yield Estimation of Integrated Circuits. DAC (2014)