Zeye Liu

Publication Activity (10 Years)

Years Active: 2016-2023
Publications (10 Years): 20

Top Topics

Energy Efficient

Top Venues

Publications

Chenlei Fang, Qicheng Huang, Zeye Liu, Ruizhou Ding, Ronald D. Blanton
Efficient Test Chip Design via Smart Computation. ACM Trans. Design Autom. Electr. Syst. 28 (2) (2023)
Zeye Liu, R. D. Shawn Blanton
High Defect-Density Yield Learning using Three-Dimensional Logic Test Chips. ITC (2020)
Ruizhou Ding, Zeye Liu, Ting-Wu Chin, Diana Marculescu, R. D. (Shawn) Blanton
FLightNNs: Lightweight Quantized Deep Neural Networks for Fast and Accurate Inference. DAC (2019)
Zeye Liu, Qicheng Huang, Chenlei Fang, R. D. (Shawn) Blanton
Improving Test Chip Design Efficiency via Machine Learning. ITC (2019)
Ruizhou Ding, Ting-Wu Chin, Zeye Liu, Diana Marculescu
Regularizing Activation Distribution for Training Binarized Deep Networks. CVPR (2019)
Ruizhou Ding, Ting-Wu Chin, Zeye Liu, Diana Marculescu
Regularizing Activation Distribution for Training Binarized Deep Networks. CoRR (2019)
Ruizhou Ding, Zeye Liu, Ting-Wu Chin, Diana Marculescu, Ronald D. Blanton
FLightNNs: Lightweight Quantized Deep Neural Networks for Fast and Accurate Inference. CoRR (2019)
Ben Niewenhuis, Balaji Ravikumar, Zeye Liu, R. D. Shawn Blanton
Path Delay Test of the Carnegie Mellon Logic Characterization Vehicle. VTS (2019)
Qicheng Huang, Chenlei Fang, Zeye Liu, Ruizhou Ding, R. D. Shawn Blanton
IPSA: Integer Programming via Sparse Approximation for Efficient Test-Chip Design. ICCD (2019)
Danielle Duvalsaint, Zeye Liu, Ananya Ravikumar, Ronald D. Blanton
Characterization of Locked Sequential Circuits via ATPG. ITC-Asia (2019)
Abhinav Goel, Zeye Liu, Ronald D. Blanton
CompactNet: High Accuracy Deep Neural Network Optimized for On-Chip Implementation. IEEE BigData (2018)
Ruizhou Ding, Zeye Liu, R. D. (Shawn) Blanton, Diana Marculescu
Lightening the Load with Highly Accurate Storage- and Energy-Efficient LightNNs. ACM Trans. Reconfigurable Technol. Syst. 11 (3) (2018)
Ruizhou Ding, Zeye Liu, R. D. (Shawn) Blanton, Diana Marculescu
Quantized deep neural networks for energy efficient hardware-based inference. ASP-DAC (2018)
Zeye Liu, Ronald D. Blanton
Back-End Layout Reflection for Test Chip Design. ICCD (2018)
Ruizhou Ding, Zeye Liu, Rongye Shi, Diana Marculescu, R. D. (Shawn) Blanton
LightNN: Filling the Gap between Conventional Deep Neural Networks and Binarized Networks. CoRR (2018)
Zeye Liu, Phillip Fynan, Ronald D. Blanton
Front-end layout reflection for test chip design. ITC (2017)
Ruizhou Ding, Zeye Liu, Rongye Shi, Diana Marculescu, R. D. (Shawn) Blanton
LightNN: Filling the Gap between Conventional Deep Neural Networks and Binarized Networks. ACM Great Lakes Symposium on VLSI (2017)
Soumya Mittal, Zeye Liu, Ben Niewenhuis, R. D. (Shawn) Blanton
Test chip design for optimal cell-aware diagnosability. ITC (2016)
Zeye Liu, Ben Niewenhuis, Soumya Mittal, R. D. (Shawn) Blanton
Achieving 100% cell-aware coverage by design. DATE (2016)
Phillip Fynan, Zeye Liu, Benjamin Niewenhuis, Soumya Mittal, Marcin Strajwas, R. D. (Shawn) Blanton
Logic characterization vehicle design reflection via layout rewiring. ITC (2016)