Xuan Zeng

ORCID

Publication Activity (10 Years)

Years Active: 1999-2024
Publications (10 Years): 155

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

DAC

DATE

ISCAS

Publications

Tianchen Gu, Jiaqi Wang, Zhaori Bi, Changhao Yan, Fan Yang, Yajie Qin, Tao Cui, Xuan Zeng
tSS-BO: Scalable Bayesian Optimization for Analog Circuit Sizing via Truncated Subspace Sampling. DATE (2024)
Yuan Meng, Ruiyu Lyu, Zhaori Bi, Changhao Yan, Fan Yang, Wenchuang Hu, Dian Zhou, Xuan Zeng
Circuits Physics Constrained Predictor of Static IR Drop with Limited Data. DATE (2024)
Xuyang Zhao, Zhaori Bi, Changhao Yan, Fan Yang, Ye Lu, Dian Zhou, Xuan Zeng
Asynchronous Batch Constrained Multi-Objective Bayesian Optimization for Analog Circuit Sizing. ASPDAC (2024)
Ruiyu Lyu, Yuan Meng, Aidong Zhao, Zhaori Bi, Keren Zhu, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng
A Study on Exploring and Exploiting the High-dimensional Design Space for Analog Circuit Design Automation : (Invited Paper). ASPDAC (2024)
Nanlin Guo, Fulin Peng, Jiahe Shi, Fan Yang, Jun Tao, Xuan Zeng
Yield Optimization for Analog Circuits over Multiple Corners via Bayesian Neural Networks: Enhancing Circuit Reliability under Environmental Variation. ACM Trans. Design Autom. Electr. Syst. 29 (1) (2024)
Aidong Zhao, Tianchen Gu, Zhaori Bi, Fan Yang, Changhao Yan, Xuan Zeng, Zixiao Lin, Wenchuang Walter Hu, Dian Zhou
PBO: Dynamic Domain Decomposition-based Parallel Bayesian Optimization for Large-scale Analog Circuit Sizing. ACM Trans. Design Autom. Electr. Syst. 29 (3) (2024)
Zhaoting Chen, Junzhe Cai, Changhao Yan, Zhaori Bi, Yuzhe Ma, Bei Yu, Wenchuang Walter Hu, Dian Zhou, Xuan Zeng
pNeurFill: Enhanced Neural Network Model-Based Dummy Filling Synthesis With Perimeter Adjustment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43 (2) (2024)
Zihao Chen, Songlei Meng, Fan Yang, Li Shang, Xuan Zeng
MACRO: Multi-agent Reinforcement Learning-based Cross-layer Optimization of Operational Amplifier. ASPDAC (2024)
Tianchen Gu, Wangzhen Li, Aidong Zhao, Zhaori Bi, Xudong Li, Fan Yang, Changhao Yan, Wenchuang Walter Hu, Dian Zhou, Tao Cui, Xin Liu, Zaikun Zhang, Xuan Zeng
BBGP-sDFO: Batch Bayesian and Gaussian Process Enhanced Subspace Derivative Free Optimization for High-Dimensional Analog Circuit Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43 (2) (2024)
Yiting Liu, Hai Zhou, Jia Wang, Fan Yang, Xuan Zeng, Li Shang
Hierarchical Graph Learning-Based Floorplanning With Dirichlet Boundary Conditions. IEEE Trans. Very Large Scale Integr. Syst. 32 (5) (2024)
Lihao Liu, Fan Yang, Li Shang, Xuan Zeng
GNN-Cap: Chip-Scale Interconnect Capacitance Extraction Using Graph Neural Network. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43 (4) (2024)
Jialin Lu, Yijie Li, Fan Yang, Li Shang, Xuan Zeng
High-Level Topology Synthesis Method for Δ-Σ Modulators via Bi-Level Bayesian Optimization. IEEE Trans. Circuits Syst. II Express Briefs 70 (12) (2023)
Ruiyao Pu, Yiwei Sun, Pei-Hsin Ho, Fan Yang, Li Shang, Xuan Zeng
Sphinx: A Hybrid Boolean Processor-FPGA Hardware Emulation System. ICCAD (2023)
Chunqiao Li, Chengtao An, Zhengqi Gao, Fan Yang, Yangfeng Su, Xuan Zeng
Unleashing the Power of Graph Spectral Sparsification for Power Grid Analysis via Incomplete Cholesky Factorization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (9) (2023)
Zhengqi Gao, Fa Wang, Jun Tao, Yangfeng Su, Xuan Zeng, Xin Li
Correlated Bayesian Model Fusion: Efficient High-Dimensional Performance Modeling of Analog/RF Integrated Circuits Over Multiple Corners. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (2) (2023)
Chengtao An, Chunqiao Li, Xiangqi Li, Yangfeng Su, Fan Yang, Xuan Zeng
FPDsim: A Structural Simulator For Power Grid Analysis Of Flat Panel Display. DAC (2023)
Jiangli Huang, Chuyu Wang, Yuyang Yan, Cong Tao, Fan Yang, Changhao Yan, Wenchuang Walter Hu, Dian Zhou, Xuan Zeng
An Analog Circuit Building Block Generator via Nested Multi-Fidelity Modeling. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (8) (2023)
Zihao Chen, Songlei Meng, Fan Yang, Li Shang, Xuan Zeng
TOTAL: Topology Optimization of Operational Amplifier via Reinforcement Learning. ISQED (2023)
Cuiyang Ding, Yijing Zhou, Wei Cai, Xuan Zeng, Changhao Yan
A path integral Monte Carlo (PIMC) method based on Feynman-Kac formula for electrical impedance tomography. J. Comput. Phys. 476 (2023)
Jialin Lu, Liangbo Lei, Jiangli Huang, Fan Yang, Li Shang, Xuan Zeng
Automatic Op-Amp Generation From Specification to Layout. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (12) (2023)
Zihao Chen, Fan Yang, Li Shang, Xuan Zeng
Automated and Agile Design of Layout Hotspot Detector via Neural Architecture Search. DATE (2023)
Aidong Zhao, Xianan Wang, Zixiao Lin, Zhaori Bi, Xudong Li, Changhao Yan, Fan Yang, Li Shang, Dian Zhou, Xuan Zeng
cVTS: A Constrained Voronoi Tree Search Method for High Dimensional Analog Circuit Synthesis. DAC (2023)
Biao He, Shuhan Zhang, Yifan Wang, Tianning Gao, Fan Yang, Changhao Yan, Dian Zhou, Zhaori Bi, Xuan Zeng
A Batched Bayesian Optimization Approach for Analog Circuit Synthesis via Multi-Fidelity Modeling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (2) (2023)
Shuyuan Sun, Fan Yang, Bei Yu, Li Shang, Xuan Zeng
Efficient ILT via Multi-level Lithography Simulation. DAC (2023)
Yiting Liu, Ziyi Ju, Zhengming Li, Mingzhi Dong, Hai Zhou, Jia Wang, Fan Yang, Xuan Zeng, Li Shang
GraphPlanner: Floorplanning with Graph Neural Network. ACM Trans. Design Autom. Electr. Syst. 28 (2) (2023)
Jun Tao, Handi Yu, Yangfeng Su, Dian Zhou, Xuan Zeng, Xin Li
Correlated Rare Failure Analysis via Asymptotic Probability Evaluation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (4) (2022)
Zhengqi Gao, Jun Tao, Yangfeng Su, Dian Zhou, Xuan Zeng, Xin Li
Fast Statistical Analysis of Rare Failure Events With Truncated Normal Distribution in High-Dimensional Variation Space. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (3) (2022)
Jingyao Zhao, Changhao Yan, Zhaori Bi, Fan Yang, Xuan Zeng, Dian Zhou
A Novel and Efficient Bayesian Optimization Approach for Analog Designs with Multi-Testbench. ASP-DAC (2022)
Xu Fu, Changhao Yan, Zhaori Bi, Fan Yang, Dian Zhou, Xuan Zeng
A Batch Bayesian Optimization Approach For Analog Circuit Synthesis Based On Multi-Points Selection Criterion. ISCAS (2022)
Shuhan Zhang, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng
An Efficient Batch-Constrained Bayesian Optimization Approach for Analog Circuit Synthesis via Multiobjective Acquisition Ensemble. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (1) (2022)
Yifan Wang, Zhaori Bi, Yuxue Xie, Tao Wu, Xuan Zeng, Shuang Chen, Dian Zhou
Learning From Highly Confident Samples for Automatic Knee Osteoarthritis Severity Assessment: Data From the Osteoarthritis Initiative. IEEE J. Biomed. Health Informatics 26 (3) (2022)
Longlong Yang, Cuiyang Ding, Changhao Yan, Dian Zhou, Xuan Zeng
A High-Precision Stochastic Solver for Steady-State Thermal Analysis with Fourier Heat Transfer Robin Boundary Conditions. ICCAD (2022)
Xiaodong Wang, Changhao Yan, Yuzhe Ma, Bei Yu, Fan Yang, Dian Zhou, Xuan Zeng
Analog Circuit Yield Optimization via Freeze-Thaw Bayesian Optimization Technique. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (11) (2022)
Yiting Liu, Ziyi Ju, Zhengming Li, Mingzhi Dong, Hai Zhou, Jia Wang, Fan Yang, Xuan Zeng, Li Shang
Floorplanning with graph attention. DAC (2022)
Hao Geng, Haoyu Yang, Lu Zhang, Fan Yang, Xuan Zeng, Bei Yu
Hotspot Detection via Attention-Based Deep Layout Metric Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (8) (2022)
Hao Jiang, Fan Yang, Changhao Yan, Xuan Zeng
SAT-based Scheduling Algorithm for High-level Synthesis Considering Resource Sharing. ISCAS (2022)
Xiaodong Wang, Changhao Yan, Fan Yang, Dian Zhou, Xuan Zeng
An efficient yield optimization method for analog circuits via gaussian process classification and varying-sigma sampling. DAC (2022)
Ran Chen, Wei Zhong, Haoyu Yang, Hao Geng, Fan Yang, Xuan Zeng, Bei Yu
Faster Region-Based Hotspot Detection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (3) (2022)
Cuiyang Ding, Changhao Yan, Xuan Zeng, Wei Cai
A Parallel Iterative Probabilistic Method for Mixed Problems of Laplace Equations with the Feynman-Kac Formula of Killed Brownian Motions. SIAM J. Sci. Comput. 44 (5) (2022)
Jialin Lu, Liangbo Lei, Fan Yang, Li Shang, Xuan Zeng
Topology Optimization of Operational Amplifier in Continuous Space via Graph Embedding. DATE (2022)
Shuhan Zhang, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng
LinEasyBO: Scalable Bayesian Optimization Approach for Analog Circuit Synthesis via One-Dimensional Subspaces. MLCAD (2022)
Shuyuan Sun, Yiyang Jiang, Fan Yang, Xuan Zeng
Adversarial Sample Generation for Lithography Hotspot Detection. ISCAS (2022)
Yiyang Jiang, Fan Yang, Bei Yu, Dian Zhou, Xuan Zeng
Efficient Layout Hotspot Detection via Neural Architecture Search. ACM Trans. Design Autom. Electr. Syst. 27 (6) (2022)
Shuyuan Sun, Yiyang Jiang, Fan Yang, Bei Yu, Xuan Zeng
Efficient Hotspot Detection via Graph Neural Network. DATE (2022)
Yan Wang, Changhao Yan, Dian Zhou, Xuan Zeng
High-Dimensional Bayesian Optimization for Automated Analog Circuit Design via Add-Graph Structure. ASICON (2021)
Junzhe Cai, Changhao Yan, Yudong Tao, Yibo Lin, Sheng-Guo Wang, David Z. Pan, Xuan Zeng
A Novel and Unified Full-Chip CMP Model Aware Dummy Fill Insertion Framework With SQP-Based Optimization Method. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40 (3) (2021)
Jialin Lu, Liangbo Lei, Fan Yang, Changhao Yan, Xuan Zeng
Automated Compensation Scheme Design for Operational Amplifier via Bayesian Optimization. DAC (2021)
Junzhe Cai, Changhao Yan, Yuzhe Ma, Bei Yu, Dian Zhou, Xuan Zeng
NeurFill: Migrating Full-Chip CMP Simulators to Neural Networks for Model-Based Dummy Filling Synthesis. DAC (2021)
Jiahui Hu, Changhao Yan, Chao Guo, Ronggui Jiang, Dian Zhou, Xuan Zeng
A Fast Aging-aware Static Timing Analysis Prediction Frame of Digital Integrated Circuits. ASICON (2021)
Yiyang Jiang, Fan Yang, Bei Yu, Dian Zhou, Xuan Zeng
Efficient Layout Hotspot Detection via Binarized Residual Neural Network Ensemble. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40 (7) (2021)
Jiangli Huang, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng
A Robust Batch Bayesian Optimization for Analog Circuit Synthesis via Local Penalization. ASP-DAC (2021)
Jiangli Huang, Shuhan Zhang, Cong Tao, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng
Bayesian Optimization Approach for Analog Circuit Design Using Multi-Task Gaussian Process. ISCAS (2021)
Zhengqi Gao, Zihao Chen, Jun Tao, Yangfeng Su, Dian Zhou, Xuan Zeng
Bayesian Inference on Introduced General Region: An Efficient Parametric Yield Estimation Method for Integrated Circuits. ASP-DAC (2021)
Cheng Zeng, Fan Yang, Xuan Zeng
Accelerate Logic Re-simulation on GPU via Gate/Event Parallelism and State Compression. ICCAD (2021)
Shuhan Zhang, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng
An Efficient Batch Constrained Bayesian Optimization Approach for Analog Circuit Synthesis via Multi-objective Acquisition Ensemble. CoRR (2021)
Shuhan Zhang, Fan Yang, Dian Zhou, Xuan Zeng
An Efficient Asynchronous Batch Bayesian Optimization Approach for Analog Circuit Synthesis. CoRR (2021)
Hao Geng, Fan Yang, Xuan Zeng, Bei Yu
When Wafer Failure Pattern Classification Meets Few-shot Learning and Self-Supervised Learning. ICCAD (2021)
Shuhan Zhang, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng
LinEasyBO: Scalable Bayesian Optimization Approach for Analog Circuit Synthesis via One-Dimensional Subspaces. CoRR (2021)
Binwu Zhu, Ran Chen, Xinyun Zhang, Fan Yang, Xuan Zeng, Bei Yu, Martin D. F. Wong
Hotspot Detection via Multi-task Learning and Transformer Encoder. ICCAD (2021)
Yue Shen, Changhao Yan, Sheng-Guo Wang, Dian Zhou, Xuan Zeng
An Efficient Yield Estimation Method for Layouts of High Dimensional and High Sigma SRAM Arrays. DATE (2021)
Yingqi Li, Fan Yang, Changhao Yan, Xuan Zeng
Efficient High-Level Synthesis of Approximate Computing Circuits via Multi-fidelity Modeling. ASICON (2021)
Jiahe Shi, Zhengqi Gao, Jun Tao, Yangfeng Su, Dian Zhou, Xuan Zeng
Multi-Corner Parametric Yield Estimation via Bayesian Inference on Bernoulli Distribution with Conjugate Prior. ISCAS (2020)
Hao Geng, Haoyu Yang, Lu Zhang, Jin Miao, Fan Yang, Xuan Zeng, Bei Yu
Hotspot Detection via Attention-based Deep Layout Metric Learning. ICCAD (2020)
Weijing Wen, Fan Yang, Yangfeng Su, Dian Zhou, Xuan Zeng
Learning Low-Rank Structured Sparsity in Recurrent Neural Networks. ISCAS (2020)
Yufeng Li, Yan Li, I-Chyn Wey, Deqiang Cheng, Fan Yang, Xuan Zeng, Jie Chen
Improved Low-Power Cost-Effective DCT Implementation Based on Markov Random Field and Stochastic Logic. IEEE Trans. Circuits Syst. Video Technol. 30 (10) (2020)
Shuhan Zhang, Fan Yang, Dian Zhou, Xuan Zeng
Bayesian Methods for the Yield Optimization of Analog and SRAM Circuits. ASP-DAC (2020)
Fulin Peng, Handi Yu, Jun Tao, Yangfeng Su, Dian Zhou, Xuan Zeng, Xin Li
Efficient Statistical Analysis for Correlated Rare Failure Events via Asymptotic Probability Approximation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (12) (2020)
Biao He, Shuhan Zhang, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng
An Efficient Bayesian Optimization Approach for Analog Circuit Synthesis via Sparse Gaussian Process Modeling. DATE (2020)
Xiaodong Wang, Tianchen Gu, Changhao Yan, Xiulong Wu, Fan Yang, Sheng-Guo Wang, Dian Zhou, Xuan Zeng
An Efficient and Robust Yield Optimization Method for High-dimensional SRAM Circuits. DAC (2020)
Binbin Liu, Fan Yang, Dian Zhou, Xuan Zeng
An Efficient Memory Partitioning Approach for Multi-Pattern Data Access in STT-RAM. ISCAS (2020)
Yiyang Jiang, Fan Yang, Hengliang Zhu, Dian Zhou, Xuan Zeng
Nonlinear CNN: improving CNNs with quadratic convolutions. Neural Comput. Appl. 32 (12) (2020)
Zhengqi Gao, Jun Tao, Dian Zhou, Xuan Zeng
Efficient Parametric Yield Estimation Over Multiple Process Corners via Bayesian Inference Based on Bernoulli Distribution. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (10) (2020)
Renjian Pan, Jun Tao, Yangfeng Su, Dian Zhou, Xuan Zeng, Xin Li
Analog/RF Post-silicon Tuning via Bayesian Optimization. ACM Trans. Design Autom. Electr. Syst. 25 (1) (2020)
Zhengqi Gao, Jun Tao, Yangfeng Su, Dian Zhou, Xuan Zeng
Projection based Active Gaussian Process Regression for Pareto Front Modeling. CoRR (2020)
Jialin Lu, Shuhan Zhang, Fan Yang, Dian Zhou, Xuan Zeng
A Mixed-Variable Bayesian Optimization Approach for Analog Circuit Synthesis. ISCAS (2020)
Zhengqi Gao, Jun Tao, Yangfeng Su, Dian Zhou, Xuan Zeng, Xin Li
Efficient Rare Failure Analysis Over Multiple Corners via Correlated Bayesian Inference. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (10) (2020)
Shuhan Zhang, Fan Yang, Dian Zhou, Xuan Zeng
An Efficient Asynchronous Batch Bayesian Optimization Approach for Analog Circuit Synthesis. DAC (2020)
Zhengqi Gao, Jun Tao, Fan Yang, Yangfeng Su, Dian Zhou, Xuan Zeng
Efficient Performance Trade-off Modeling for Analog Circuit based on Bayesian Neural Network. ICCAD (2019)
Changyong Liu, Nianlong Liu, Zhiting Lin, Xiulong Wu, Chunyu Peng, Qiang Zhao, Xuan Li, Junning Chen, Xuan Zeng, Xiangdong Hu
A single event upset tolerant latch with parallel nodes. IEICE Electron. Express 16 (11) (2019)
Shuhan Zhang, Wenlong Lyu, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng, Xiangdong Hu
An Efficient Multi-fidelity Bayesian Optimization Approach for Analog Circuit Synthesis. CoRR (2019)
Huaidong Gao, Fan Yang, Dian Zhou, Xuan Zeng
Parallel Global Placement on CPU via Parallel Reduction. ASICON (2019)
Chunyu Peng, Jiati Huang, Changyong Liu, Qiang Zhao, Songsong Xiao, Xiulong Wu, Zhiting Lin, Junning Chen, Xuan Zeng
Radiation-Hardened 14T SRAM Bitcell With Speed and Power Optimized for Space Application. IEEE Trans. Very Large Scale Integr. Syst. 27 (2) (2019)
Shuhan Zhang, Wenlong Lyu, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng
Bayesian Optimization Approach for Analog Circuit Synthesis Using Neural Network. DATE (2019)
Hao Jiang, Yang Fan, Xuan Zeng
Scheduling Algorithm Based on System of Difference Constraints Using Network Flow. ASICON (2019)
Xiang Ge, Fan Yang, Hengliang Zhu, Xuan Zeng, Dian Zhou
An Efficient FPGA Implementation of Orthogonal Matching Pursuit With Square-Root-Free QR Decomposition. IEEE Trans. Very Large Scale Integr. Syst. 27 (3) (2019)
Yiyang Jiang, Fan Yang, Hengliang Zhu, Bei Yu, Dian Zhou, Xuan Zeng
Efficient Layout Hotspot Detection via Binarized Residual Neural Network. DAC (2019)
Wensong Li, Fan Yang, Hengliang Zhu, Xuan Zeng, Dian Zhou
An Efficient Memory Partitioning Approach for Multi-Pattern Data Access via Data Reuse. ACM Trans. Reconfigurable Technol. Syst. 12 (1) (2019)
Jun Tao, Yangfeng Su, Dian Zhou, Xuan Zeng, Xin Li
Graph-Constrained Sparse Performance Modeling for Analog Circuit Optimization via SDP Relaxation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38 (8) (2019)
Changyong Liu, Zhiting Lin, Xiulong Wu, Chunyu Peng, Qiang Zhao, Xuan Li, Junning Chen, Xuan Zeng, Xiangdong Hu
An inverter chain with parallel output nodes for eliminating single-event transient pulse. IEICE Electron. Express 16 (4) (2019)
Weijing Wen, Fan Yang, Yangfeng Su, Dian Zhou, Xuan Zeng
Learning Sparse Patterns in Deep Neural Networks. ASICON (2019)
Xin Wei, Changhao Yan, Hai Zhou, Dian Zhou, Xuan Zeng
An Efficient FPGA-based Floating Random Walk Solver for Capacitance Extraction using SDAccel. DATE (2019)
Ran Chen, Wei Zhong, Haoyu Yang, Hao Geng, Xuan Zeng, Bei Yu
Faster Region-based Hotspot Detection. DAC (2019)
Shuhan Zhang, Wenlong Lyu, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng, Xiangdong Hu
An Efficient Multi-fidelity Bayesian Optimization Approach for Analog Circuit Synthesis. DAC (2019)
Shuhan Zhang, Wenlong Lyu, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng
Bayesian Optimization Approach for Analog Circuit Synthesis Using Neural Network. CoRR (2019)
Wensong Li, Fan Yang, Hengliang Zhu, Xuan Zeng, Dian Zhou
An efficient data reuse strategy for multi-pattern data access. ICCAD (2018)
Yan Li, Yufeng Li, I-Chyn Wey, Jianhao Hu, Fan Yang, Xuan Zeng, Xiaoxue Jiang, Jie Chen
Low-Power Noise-Immune Nanoscale Circuit Design Using Coding-Based Partial MRF Method. IEEE J. Solid State Circuits 53 (8) (2018)
Yan Li, Yufeng Li, Jie Han, Jianhao Hu, Fan Yang, Xuan Zeng, Bruce F. Cockburn, Jie Chen
Feedback-Based Low-Power Soft-Error-Tolerant Design for Dual-Modular Redundancy. IEEE Trans. Very Large Scale Integr. Syst. 26 (8) (2018)
Changyong Liu, Chunyu Peng, Zhiting Lin, Xiulong Wu, Ziyang Chen, Qiang Zhao, Xuan Li, Junning Chen, Xuan Zeng, Xiangdong Hu
A dual-output hardening design of inverter chain for P-hit single-event transient pulse elimination. IEICE Electron. Express 15 (15) (2018)
Jinyuan Zhai, Changhao Yan, Sheng-Guo Wang, Dian Zhou, Hai Zhou, Xuan Zeng
An Efficient Non-Gaussian Sampling Method for High Sigma SRAM Yield Analysis. ACM Trans. Design Autom. Electr. Syst. 23 (3) (2018)
Yishi Yang, Hengliang Zhu, Zhaori Bi, Changhao Yan, Dian Zhou, Yangfeng Su, Xuan Zeng
Smart-MSP: A Self-Adaptive Multiple Starting Point Optimization Approach for Analog Circuit Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37 (3) (2018)

Xuan Zeng.css-eqlu8i{font-size:small;padding-left:4px;}

Publication Activity (10 Years)

Top Topics

Top Venues

Xuan Zeng