Jia Wang

Publication Activity (10 Years)

Years Active: 2004-2024
Publications (10 Years): 2

Top Topics

Bp Neural Network

Boundary Conditions

Top Venues

ACM Trans. Design Autom. Electr. Syst.

IEEE Trans. Very Large Scale Integr. Syst.

Publications

Yiting Liu, Hai Zhou, Jia Wang, Fan Yang, Xuan Zeng, Li Shang
Hierarchical Graph Learning-Based Floorplanning With Dirichlet Boundary Conditions. IEEE Trans. Very Large Scale Integr. Syst. 32 (5) (2024)
Yiting Liu, Ziyi Ju, Zhengming Li, Mingzhi Dong, Hai Zhou, Jia Wang, Fan Yang, Xuan Zeng, Li Shang
GraphPlanner: Floorplanning with Graph Neural Network. ACM Trans. Design Autom. Electr. Syst. 28 (2) (2023)
Jie Wu, Jia Wang, Kun Li, Hai Zhou, Qin Lv, Li Shang, Yihe Sun
Large-Scale Energy Storage System Design and Optimization for Emerging Electric-Drive Vehicles. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (3) (2013)
Debasish Das, Jia Wang, Hai Zhou
iRetILP: an efficient incremental algorithm for min-period retiming under general delay model. ASP-DAC (2010)
Jia Wang, Kun Li, Qin Lv, Hai Zhou, Li Shang
Hybrid energy storage system integration for vehicles. ISLPED (2010)
Jia Wang, Hai Zhou
Exploring adjacency in floorplanning. ASP-DAC (2009)
Jia Wang, Debasish Das, Hai Zhou
Gate Sizing by Lagrangian Relaxation Revisited. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28 (7) (2009)
Jia Wang, Hai Zhou
Risk aversion min-period retiming under process variations. ASP-DAC (2009)
Jia Wang, Hai Zhou
An efficient incremental algorithm for min-area retiming. DAC (2008)
Jia Wang, Hai Zhou
Linear constraint graph for floorplan optimization with soft blocks. ICCAD (2008)
Jia Wang, Debasish Das, Hai Zhou
Gate sizing by Lagrangian relaxation revisited. ICCAD (2007)
Jia Wang, Ming-Yang Kao, Hai Zhou
Address generation for nanowire decoders. ACM Great Lakes Symposium on VLSI (2007)
Jia Wang, Hai Zhou
Optimal Jumper Insertion for Antenna Avoidance Considering Antenna Charge Sharing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (8) (2007)
Zhenyu (Peter) Gu, Jia Wang, Robert P. Dick, Hai Zhou
Unified Incremental Physical-Level and High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (9) (2007)
Jia Wang, Hai Zhou, Ping-Chih Wu
Processing Rate Optimization by Sequential System Floorplanning. ISQED (2006)
Chuan Lin, Jia Wang, Hai Zhou
Clustering for Processing Rate Optimization. IEEE Trans. Very Large Scale Integr. Syst. 14 (11) (2006)
Jia Wang, Hai Zhou
Optimal jumper insertion for antenna avoidance under ratio upper-bound. DAC (2006)
Zhenyu (Peter) Gu, Yonghong Yang, Jia Wang, Robert P. Dick, Li Shang
TAPHS: thermal-aware unified physical-level and high-level synthesis. ASP-DAC (2006)
Zhenyu (Peter) Gu, Jia Wang, Robert P. Dick, Hai Zhou
Incremental exploration of the combined physical and behavioral design space. DAC (2005)
Jia Wang, Hai Zhou
Interconnect estimation without packing via ACG floorplans. ASP-DAC (2005)
Chuan Lin, Jia Wang, Hai Zhou
Clustering for processing rate optimization. ICCAD (2005)
Hai Zhou, Jia Wang
ACG-Adjacent Constraint Graph for General Floorplans. ICCD (2004)
Jia Wang, Hai Zhou
Minimal period retiming under process variations. ACM Great Lakes Symposium on VLSI (2004)