Yihe Sun

Publication Activity (10 Years)

Years Active: 2001-2024
Publications (10 Years): 1

Top Topics

Building Blocks

Power Electronics

Top Venues

IEEE Trans. Ind. Electron.

Publications

Xiaoqiang Li, Chu Chen, Yihe Sun, Hao Cheng
Low/Middle-Frequency Positive External- Damping Design Under Self-Stability Constraint for Inner Control Loop of Grid-Forming Converters. IEEE Trans. Ind. Electron. 71 (5) (2024)
Jie Wu, Jia Wang, Kun Li, Hai Zhou, Qin Lv, Li Shang, Yihe Sun
Large-Scale Energy Storage System Design and Optimization for Emerging Electric-Drive Vehicles. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (3) (2013)
Bo Yu, Rosa H. M. Chan, Terrence S. T. Mak, Yihe Sun, Chi-Sang Poon
On-Chip Systolic Networks for Real-Time Tracking of Pairwise Correlations Between Neurons in a Large-Scale Network. IEEE Trans. Biomed. Eng. 60 (1) (2013)
Zheng Li, Moustafa Mohamed, Xi Chen, Eric Dudley, Ke Meng, Li Shang, Alan Rolf Mickelson, Russ Joseph, Manish Vachharajani, Brian Schwartz, Yihe Sun
Reliability Modeling and Management of Nanophotonic On-Chip Networks. IEEE Trans. Very Large Scale Integr. Syst. 20 (1) (2012)
Allann Al-armaghany, Bo Yu, Terrence S. T. Mak, Kin-Fai Tong, Yihe Sun
Feasibility study for future implantable neural-silicon interface devices. EMBC (2011)
Bo Yu, Terrence S. T. Mak, Leslie Smith, Yihe Sun, Alex Yakovlev, Chi-Sang Poon
Memory efficient on-line streaming for multichannel spike train analysis. EMBC (2011)
Junli Gu, Steven S. Lumetta, Rakesh Kumar, Yihe Sun
MOPED: Orchestrating interprocess message data on CMPs. HPCA (2011)
Bo Yu, Terrence S. T. Mak, Yihe Sun, Chi-Sang Poon
Real-time neuronal networks reconstruction using hierarchical systolic arrays. EMBC (2011)
Junli Gu, Yihe Sun, Steven S. Lumetta, Rakesh Kumar
MOPED: Accelerating Data Communication on Future CMPs. IEEE Micro 31 (4) (2011)
Bo Yu, Terrence S. T. Mak, Xiangyu Li, Fei Xia, Alexandre Yakovlev, Yihe Sun, Chi-Sang Poon
Real-Time FPGA-Based Multichannel Spike Sorting Using Hebbian Eigenfilters. IEEE J. Emerg. Sel. Topics Circuits Syst. 1 (4) (2011)
Bo Yu, Terrence S. T. Mak, Xiangyu Li, Fei Xia, Alexandre Yakovlev, Yihe Sun, Chi-Sang Poon
A Reconfigurable Hebbian Eigenfilter for Neurophysiological Spike Train Analysis. FPL (2010)
Junli Gu, Rakesh Kumar, Steven S. Lumetta, Yihe Sun
Accelerating data movement on future chip multi-processors. IFMT (2010)
Zheng Li, Moustafa Mohamed, Hongyu Zhou, Li Shang, Alan Rolf Mickelson, Dejan Filipovic, Manish Vachharajani, Wounjhang Park, Yihe Sun
Global On-Chip Coordination at Light Speed. IEEE Des. Test Comput. 27 (4) (2010)
Moustafa Mohamed, Zheng Li, Xi Chen, Li Shang, Alan Rolf Mickelson, Manish Vachharajani, Yihe Sun
Power-efficient variation-aware photonic on-chip network management. ISLPED (2010)
Yang Xu, Hu He, Yihe Sun
A Novel Low Energy Scheduling Algorithm for Clustered Very Long Instruction Word Architectures. J. Low Power Electron. 5 (2) (2009)
Zheng Li, Jie Wu, Li Shang, Alan Rolf Mickelson, Manish Vachharajani, Dejan Filipovic, Wounjhang Park, Yihe Sun
A high-performance low-power nanophotonic on-chip network. ISLPED (2009)
Zheng Li, Dan Fay, Alan Rolf Mickelson, Li Shang, Manish Vachharajani, Dejan Filipovic, Wounjhang Park, Yihe Sun
Spectrum: a hybrid nanophotonic-electric on-chip network. DAC (2009)
Zheng Shen, Hu He, Yihe Sun
Simultaneous Multithreading VLIW DSP Architecture with Dynamic Dispatch Mechanism. DSD (2009)
Zheng Li, Jie Wu, Li Shang, Robert P. Dick, Yihe Sun
Latency criticality aware on-chip communication. DATE (2009)
Adriel Cheng, Cheng-Chew Lim, Yihe Sun, Hu He, Zhixiong Zhou, Ting Lei
Using Genetic Evolutionary Software Application Testing to Verify a DSP SoC. DELTA (2008)
Zheng Li, Changyun Zhu, Li Shang, Robert P. Dick, Yihe Sun
Transaction-Aware Network-on-Chip Resource Reservation. IEEE Comput. Archit. Lett. 7 (2) (2008)
Zheng Shen, Hu He, Yanjun Zhang, Yihe Sun
A Video Specific Instruction Set Architecture for ASIP design. VLSI Design 2007 (2007)
Zhixiong Zhou, Hu He, Yanjun Zhang, Yihe Sun, Adriel Cheng
A 2-Dimension Force-Directed Scheduling Algorithm for Register-File-Connectivity Clustered VLIW Architecture. ASAP (2007)
Yang Xu, Hu He, Zhou Zhixiong, Yanjun Zhang, Yihe Sun
Heuristic on a Novel Power Management System Cooperating with Compiler. J. Low Power Electron. 3 (1) (2007)
Zheng Shen, Hu He, Yanjun Zhang, Yihe Sun
VS-ISA: A Video Specific Instruction Set Architecture for ASIP Design. IIH-MSP (2006)
Zhou Zhixiong, Yang Xu, He Hu, Yihe Sun
A Retargetable Compiler of VLIW ASIP for Media Signal Processing. ESA (2006)
Yanjun Zhang, Hu He, Yihe Sun
A new register file access architecture for software pipelining in VLIW processors. ASP-DAC (2005)
Xingjun Wu, Hongyi Chen, Yihe Sun, Weixin Gai
A Fully-Pipeline Linear Systolic Architecture for Modular Multiplier in Public-Key Crypto-Systems. J. VLSI Signal Process. 33 (1-2) (2003)
He Hu, Yihe Sun
Test-Point Selection Algorithm Using Small Signal Model for Scan-Based BIST. Asian Test Symposium (2003)
Ke Jiang, Yihe Sun
An Optimizing Search Method of Systolic Array Design. IASTED PDCS (2002)
Lei Xu, Yihe Sun, Hongyi Chen
Scan array solution for testing power and testing time. ITC (2001)