​
Login / Signup
Xingjun Wu
ORCID
Publication Activity (10 Years)
Years Active: 2003-2023
Publications (10 Years): 10
Top Topics
Convolutional Neural Network
Lightweight
Hardware Implementation
Power Analysis
Top Venues
CIS
TrustCom/BigDataSE
ISCE
ASICON
</>
Publications
</>
Wentao Xi
,
Xingjun Wu
,
Kai Zhang
A low-cost configurable hash computing circuit for PQC algorithm.
ICCNS
(2023)
Jing Ye
,
Ruijuan Li
,
Min Zhang
,
Xingjun Wu
,
Qian Yang
Elderly Nursing Monitoring System Based on DSP.
AIAM
(2022)
Dongmei Wei
,
Xingjun Wu
,
Guoqiang Bai
,
Linlin Su
,
Sufen Xu
Attention-based Efficient Lightweight Model for Accurate Real-Time Face Verification on Embedded Device.
ICCCS
(2021)
Ru Ding
,
Xuemei Tian
,
Guoqiang Bai
,
Guangda Su
,
Xingjun Wu
Hardware Implementation of Convolutional Neural Network for Face Feature Extraction.
ASICON
(2019)
Guoqiang Bai
,
Hailiang Fu
,
Wei Li
,
Xingjun Wu
Differential Power Attack on SM4 Block Cipher.
TrustCom/BigDataSE
(2018)
Yi Wu
,
Xingjun Wu
Implementation of efficient method of RSA key-pair generation algorithm.
ISCE
(2017)
Hailiang Fu
,
Guoqiang Bai
,
Xingjun Wu
A Very Compact Masked S-Box for High-Performance Implementation of SM4 Based on Composite Field.
SecureComm
(2016)
Sulong Tang
,
Liji Wu
,
Xiangmin Zhang
,
Xingjun Wu
,
Beibei Wang
A Novel Method of Correlation Power Analysis on SM4 Hardware Implementation.
CIS
(2016)
Juhua Liu
,
Guoqiang Bai
,
Xingjun Wu
Efficient Hardware Implementation of Roadrunner for Lightweight Application.
Trustcom/BigDataSE/ISPA
(2016)
Chaohui Du
,
Guoqiang Bai
,
Xingjun Wu
High-Speed Polynomial Multiplier Architecture for Ring-LWE Based Public Key Cryptosystems.
ACM Great Lakes Symposium on VLSI
(2016)
Shaohui Zhang
,
Liji Wu
,
Xiangmin Zhang
,
Xingjun Wu
,
Xiangyu Li
,
Huajun Fang
A Template Attack-Resistant Masking Scheme for RC4 Based on FPGA.
CIS
(2015)
Changming Ma
,
Xingjun Wu
,
Chun Zhang
,
Zhihua Wang
A low-power RF front-end of passive UHF RFID transponders.
APCCAS
(2008)
Xingjun Wu
,
Hongyi Chen
,
Yihe Sun
,
Weixin Gai
A Fully-Pipeline Linear Systolic Architecture for Modular Multiplier in Public-Key Crypto-Systems.
J. VLSI Signal Process.
33 (1-2) (2003)