Hu He

Publication Activity (10 Years)

Years Active: 2005-2024
Publications (10 Years): 17

Top Topics

Architectural Model

Cerebellar Model

Top Venues

Publications

Jingzhou Li, Huaiyu Chen, Wenbin Zhang, Hu He
HCRF: A Hardware Checkpoint-based Recovery Framework in light dual-core lockstep processors. ACM Great Lakes Symposium on VLSI (2024)
Hanwen Gong, Hu He, Liyang Pan, Bin Gao, Jianshi Tang, Sining Pan, Jianing Li, Peng Yao, Dabin Wu, He Qian, Huaqiang Wu
An Error-Free 64KB ReRAM-Based nvSRAM Integrated to a Microcontroller Unit Supporting Real-Time Program Storage and Restoration. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (12) (2023)
Ruihua Yu, Wenqiang Zhang, Bin Gao, Yiwen Geng, Peng Yao, Yuyi Liu, Qingtian Zhang, Jianshi Tang, Dong Wu, Hu He, Ning Deng, He Qian, Huaqiang Wu
CLEAR: a full-stack chip-in-loop emulator for analog RRAM based computing-in-memory system. Sci. China Inf. Sci. 66 (12) (2023)
Hanwen Gong, Hu He, Bin Gao, Jianshi Tang, Qingtian Zhang, He Qian, Huaqiang Wu
ACCLAIM: An End-to-End SystemC-AMS Simulation Framework for Analog In-Memory-Computing. ICTA (2023)
Hanwen Gong, Hu He, Bin Gao, Jianshi Tang, Jian Yu, Dabin Wu, Junren Chen, Qingtian Zhang, Xing Mou, He Qian, Huaqiang Wu
A 1-Mb Programming Configurable ReRAM Fully Integrating Into a 32-Bit Microcontroller Unit. IEEE Trans. Circuits Syst. II Express Briefs 70 (8) (2023)
Yanhai Jiang, Bin Gao, Jianshi Tang, Dabin Wu, Hu He, He Qian, Huaqiang Wu
HARNS: High-level Architectural Model of RRAM based Computing-in-memory NPU. ICTA (2021)
Hu He, Qilin Wang, Xu Yang, Yunlin Lei, Jia Cai, Ning Deng
A memory neural system built based on spiking neural network. Neurocomputing 442 (2021)
Liya Dong, Qilin Wang, Hu He
The Algorithm of Spiking Neural Network And Application in Poker Games. ICMSSP (2020)
Yumin Hou, Hu He, Kaveh Shamsi, Yier Jin, Dong Wu, Huaqiang Wu
On-Chip Analog Trojan Detection Framework for Microprocessor Trustworthiness. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38 (10) (2019)
Wenqiang Zhang, Xiaochen Peng, Huaqiang Wu, Bin Gao, Hu He, Youhui Zhang, Shimeng Yu, He Qian
Design Guidelines of RRAM based Neural-Processing-Unit: A Joint Device-Circuit-Algorithm Analysis. DAC (2019)
Xu Yang, Guo Liu, Songgaojun Deng, Zichao Wei, Hu He, Yingjie Shang, Ning Deng
Exploration of a mechanism to form bionic, self-growing and self-organizing neural network. Artif. Intell. Rev. 52 (1) (2019)
Xu Yang, Yumin Hou, Hu He
A Processing-in-Memory Architecture Programming Paradigm for Wireless Internet-of-Things Applications. Sensors 19 (1) (2019)
Xu Yang, Yumin Hou, Junping Ma, Hu He
CDSP: A Solution for Privacy and Security of Multimedia Information Processing in Industrial Big Data and Internet of Things. Sensors 19 (3) (2019)
Yumin Hou, Xu Wang, Jiawei Fu, Junping Ma, Hu He, Xu Yang
Improving ILP via Fused In-Order Superscalar and VLIW Instruction Dispatch Methods. J. Circuits Syst. Comput. 28 (2) (2019)
Yumin Hou, Hu He, Kaveh Shamsi, Yier Jin, Dong Wu, Huaqiang Wu
R2D2: Runtime reassurance and detection of A2 Trojan. HOST (2018)
Hu He, Xu Yang, Yanjun Zhang
On Improving Performance and Energy Efficiency for Register-File Connected Clustered VLIW Architectures for Embedded System Usage. Comput. J. 60 (9) (2017)
Yumin Hou, Hu He, Xu Yang, Deyuan Guo, Xu Wang, Jiawei Fu, Keni Qiu
FuMicro: A Fused Microarchitecture Design Integrating In-Order Superscalar and VLIW. VLSI Design 2016 (2016)
Xu Yang, Deyuan Guo, Hu He, Haijing Tang, Yanjun Zhang
An Implementation of Message-Passing Interface over VxWorks for Real-Time Embedded Multi-Core Systems. Comput. J. 57 (11) (2014)
Xu Yang, Yanjun Zhang, Dake Liu, Deyuan Guo, Hu He
Single instruction multiple data code auto generation for a very long instruction words digital signal processor in sensor-based systems. IET Wirel. Sens. Syst. 3 (2) (2013)
Xu Yang, Hu He
An Advanced Compiler Designed for a VLIW DSP for Sensors-Based Systems. Sensors 12 (4) (2012)
Yang Xu, Hu He, Yihe Sun
A Novel Low Energy Scheduling Algorithm for Clustered Very Long Instruction Word Architectures. J. Low Power Electron. 5 (2) (2009)
Zheng Shen, Hu He, Yihe Sun
Simultaneous Multithreading VLIW DSP Architecture with Dynamic Dispatch Mechanism. DSD (2009)
Adriel Cheng, Cheng-Chew Lim, Yihe Sun, Hu He, Zhixiong Zhou, Ting Lei
Using Genetic Evolutionary Software Application Testing to Verify a DSP SoC. DELTA (2008)
Zheng Shen, Hu He, Yanjun Zhang, Yihe Sun
A Video Specific Instruction Set Architecture for ASIP design. VLSI Design 2007 (2007)
Zhixiong Zhou, Hu He, Yanjun Zhang, Yihe Sun, Adriel Cheng
A 2-Dimension Force-Directed Scheduling Algorithm for Register-File-Connectivity Clustered VLIW Architecture. ASAP (2007)
Yang Xu, Hu He, Zhou Zhixiong, Yanjun Zhang, Yihe Sun
Heuristic on a Novel Power Management System Cooperating with Compiler. J. Low Power Electron. 3 (1) (2007)
Zheng Shen, Hu He, Yanjun Zhang, Yihe Sun
VS-ISA: A Video Specific Instruction Set Architecture for ASIP Design. IIH-MSP (2006)
Yanjun Zhang, Hu He, Yihe Sun
A new register file access architecture for software pipelining in VLIW processors. ASP-DAC (2005)