Russ Joseph

Publication Activity (10 Years)

Years Active: 2001-2020
Publications (10 Years): 13

Top Topics

Design Methodology

Instruction Set

Communication Protocols

Top Venues

IEEE J. Solid State Circuits

Publications

Tianyu Jia, Yuhao Ju, Russ Joseph, Jie Gu
NCPU: An Embedded Neural CPU Architecture on Resource-Constrained Low Power Devices for Real-time End-to-End Performance. MICRO (2020)
Tianyu Jia, Yijie Wei, Russ Joseph, Jie Gu
An Adaptive Clock Scheme Exploiting Instruction-Based Dynamic Timing Slack for a GPGPU Architecture. IEEE J. Solid State Circuits 55 (8) (2020)
Tianyu Jia, Russ Joseph, Jie Gu
An Adaptive Clock Management Scheme Exploiting Instruction-Based Dynamic Timing Slack for a General-Purpose Graphics Processor Unit with Deep Pipeline and Out-of-Order Execution. ISSCC (2019)
Yuanbo Fan, Simone Campanoni, Russ Joseph
Time squeezing for tiny devices. ISCA (2019)
Tianyu Jia, Russ Joseph, Jie Gu
An Instruction-Driven Adaptive Clock Management Through Dynamic Phase Scaling and Compiler Assistance for a Low Power Microprocessor. IEEE J. Solid State Circuits 54 (8) (2019)
Chao Yan, Russ Joseph
Cocoa: synergistic cache compression and error correction in capacity sensitive last level caches. MEMSYS (2018)
Tianyu Jia, Russ Joseph, Jie Gu
An Instruction Driven Adaptive Clock Phase Scaling with Timing Encoding and Online Instruction Calibration for a Low Power Microprocessor. ESSCIRC (2018)
Yuanbo Fan, Tianyu Jia, Jie Gu, Simone Campanoni, Russ Joseph
Compiler-guided instruction-level clock scheduling for timing speculative processors. DAC (2018)
Yuanbo Fan, Russ Joseph
D2M: data-driven model for fast and accurate timing error simulation in statically scheduled microprocessors. SummerSim (2017)
Tianyu Jia, Yuanbo Fan, Russ Joseph, Jie Gu
(Invited) Software-guided greybox design methodology with integrated power and clock management. MWSCAS (2017)
Tianyu Jia, Russ Joseph, Jie Gu
Greybox Design Methodology: A Program Driven Hardware Co-optimization with Ultra-Dynamic Clock Management. DAC (2017)
Tianyu Jia, Yuanbo Fan, Russ Joseph, Jie Gu
Exploration of associative power management with instruction governed operation for ultra-low power design. DAC (2016)
Chao Yan, Russ Joseph
Enabling Deep Voltage Scaling in Delay Sensitive L1 Caches. DSN (2016)
Xuejing He, Robert P. Dick, Russ Joseph
Embedded system and application aware design of deregulated energy delivery systems. CASES (2015)
Xuejing He, Robert P. Dick, Russ Joseph
Spatially- and temporally-adaptive communication protocols for zero-maintenance sensor networks relying on opportunistic energy scavenging. CODES+ISSS (2012)
Zheng Li, Moustafa Mohamed, Xi Chen, Eric Dudley, Ke Meng, Li Shang, Alan Rolf Mickelson, Russ Joseph, Manish Vachharajani, Brian Schwartz, Yihe Sun
Reliability Modeling and Management of Nanophotonic On-Chip Networks. IEEE Trans. Very Large Scale Integr. Syst. 20 (1) (2012)
Patrick G. Bridges, Dorian C. Arnold, Kevin T. Pedretti, Madhav Suresh, Feng Lu, Peter A. Dinda, Russ Joseph, Jack Lange
Virtual-machine-based emulation of future generation high-performance computing systems. Int. J. High Perform. Comput. Appl. 26 (2) (2012)
Jing Xin, Russ Joseph
Identifying and predicting timing-critical instructions to boost timing speculation. MICRO (2011)
Feng Lu, Russ Joseph, Goce Trajcevski, Song Liu
Efficient parameter variation sampling for architecture simulations. DATE (2011)
Giang Hoang, Robby Bruce Findler, Russ Joseph
Exploring circuit timing-aware language and compilation. ASPLOS (2011)
Giang Hoang, Chang Bae, Jack Lange, Lide Zhang, Peter A. Dinda, Russ Joseph
A Case for Alternative Nested Paging Models for Virtualized Systems. IEEE Comput. Archit. Lett. 9 (1) (2010)
Jing Xin, Russ Joseph
Exploiting Locality to Improve Circuit-Level Timing Speculation. IEEE Comput. Archit. Lett. 8 (2) (2009)
Lide Zhang, Lan S. Bai, Robert P. Dick, Li Shang, Russ Joseph
Process variation characterization of chip-level multiprocessors. DAC (2009)
Ke Meng, Russ Joseph, Robert P. Dick, Li Shang
Multi-optimization power management for chip multiprocessors. PACT (2008)
Changyun Zhu, Zhenyu (Peter) Gu, Li Shang, Robert P. Dick, Russ Joseph
Three-Dimensional Chip-Multiprocessor Run-Time Thermal Management. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (8) (2008)
David M. Brooks, Robert P. Dick, Russ Joseph, Li Shang
Power, Thermal, and Reliability Modeling in Nanometer-Scale Microprocessors. IEEE Micro 27 (3) (2007)
Ke Meng, Frank Huebbers, Russ Joseph, Yehea I. Ismail
Modeling and Characterizing Power Variability in Multicore Architectures. ISPASS (2007)
Meeta Sharma Gupta, Jarod L. Oatley, Russ Joseph, Gu-Yeon Wei, David M. Brooks
Understanding voltage variations in chip multiprocessors using a distributed power-delivery network. DATE (2007)
Seunghoon Kim, Robert P. Dick, Russ Joseph
Power deregulation: eliminating off-chip voltage regulation circuitry from embedded systems. CODES+ISSS (2007)
Ke Meng, Russ Joseph
Process variation aware cache leakage management. ISLPED (2006)
Russ Joseph, Margaret Martonosi, Zhigang Hu
Spectral analysis for characterizing program power and performance. ISPASS (2004)
Russ Joseph, Zhigang Hu, Margaret Martonosi
Wavelet Analysis for Microprocessor Design: Experiences with Wavelet-Based dI/dt Characterization. HPCA (2004)
Russ Joseph, David M. Brooks, Margaret Martonosi
Control Techniques to Eliminate Voltage Emergencies in High Performance Processors. HPCA (2003)
Russ Joseph, Margaret Martonosi
Run-time power estimation in high performance microprocessors. ISLPED (2001)