Jie Gu

Publication Activity (10 Years)

Years Active: 2016-2024
Publications (10 Years): 49

Top Topics

Fully Integrated

Design Methodology

Top Venues

IEEE J. Solid State Circuits

Publications

Yuhao Ju, Ganqi Xu, Jie Gu
20.4 A 28nm Physics Computing Unit Supporting Emerging Physics-Informed Neural Network and Finite Element Method for Real-Time Scientific Computing on Edge Devices. ISSCC (2024)
Zhiwei Zhong, Yijie Wei, Lance Christopher Go, Jie Gu
33.2 A Sub-1μJ/class Headset-Integrated Mind Imagery and Control SoC for VR/MR Applications with Teacher-Student CNN and General-Purpose Instruction Set Architecture. ISSCC (2024)
Xi Chen, Aly Shoukry, Tianyu Jia, Xin Zhang, Raveesh Magod, Nachiket V. Desai, Jie Gu
A 65nm Fully-integrated Fast-switching Buck Converter with Resonant Gate Drive and Automatic Tracking. CICC (2023)
Yuhao Ju, Jie Gu
A Systolic Neural CPU Processor Combining Deep Learning and General-Purpose Computing With Enhanced Data Locality and End-to-End Performance. IEEE J. Solid State Circuits 58 (1) (2023)
Xi Chen, Jiaxiang Feng, Aly Shoukry, Xin Zhang, Raveesh Magod, Nachiket V. Desai, Jie Gu
Proactive Power Regulation with Real-time Prediction and Fast Response Guardband for Fine-grained Dynamic Voltage Droop Mitigation on Digital SoCs. VLSI Technology and Circuits (2023)
Yijie Wei, Xi Chen, Jie Gu
Human Activity Recognition SoC for AR/VR with Integrated Neural Sensing, AI Classifier and Chained Infrared Communication for Multi-chip Collaboration. VLSI Technology and Circuits (2023)
Qiankai Cao, Xi Chen, Jie Gu
Development of Tropical Algebraic Accelerator with Energy Efficient Time-Domain Computing for Combinatorial Optimization and Machine Learning. ISLPED (2023)
Yijie Wei, Zhiwei Zhong, Jie Gu
Human emotion based real-time memory and computation management on resource-limited edge devices. DAC (2022)
Qiankai Cao, Jie Gu
A Sparse Convolution Neural Network Accelerator for 3D/4D Point-Cloud Image Recognition on Low Power Mobile Device with Hopping-Index Rule Book for Efficient Coordinate Management. VLSI Technology and Circuits (2022)
Yuhao Ju, Shiyu Guo, Zixuan Liu, Tianyu Jia, Jie Gu
A Differentiable Neural Computer for Logic Reasoning with Scalable Near-Memory Computing and Sparsity Based Enhancement. ESSCIRC (2022)
Yijie Wei, Xi Chen, Jie Gu
A 65nm Implantable Gesture Classification SoC for Rehabilitation with Enhanced Data Compression and Encoding for Robust Neural Network Operation Under Wireless Power Condition. CICC (2022)
Yuhao Ju, Jie Gu
A 65nm Systolic Neural CPU Processor for Combined Deep Learning and General-Purpose Computing with 95% PE Utilization, High Data Locality and Enhanced End-to-End Performance. ISSCC (2022)
Zhengyu Chen, Jie Gu
High-Throughput Dynamic Time Warping Accelerator for Time-Series Classification With Pipelined Mixed-Signal Time-Domain Computing. IEEE J. Solid State Circuits 56 (2) (2021)
Zhengyu Chen, Xi Chen, Jie Gu
15.3 A 65nm 3T Dynamic Analog RAM-Based Computing-in-Memory Macro and CNN Accelerator with Retention Enhancement, Adaptive Analog Sparsity and 44TOPS/W System Energy Efficiency. ISSCC (2021)
Yijie Wei, Qiankai Cao, Kofi Otseidu, Levi J. Hargrove, Jie Gu
A Gesture Classification SoC for Rehabilitation With ADC-Less Mixed-Signal Feature Extraction and Training Capable Neural Network Classifier. IEEE J. Solid State Circuits 56 (3) (2021)
Tianyu Jia, Yuhao Ju, Jie Gu
A Dynamic Timing Enhanced DNN Accelerator With Compute-Adaptive Elastic Clock Chain Technique. IEEE J. Solid State Circuits 56 (1) (2021)
Amin Rezaei, Jie Gu, Hai Zhou
Hybrid Memristor-CMOS Obfuscation Against Untrusted Foundries. IACR Cryptol. ePrint Arch. 2021 (2021)
Yijie Wei, Qiankai Cao, Levi J. Hargrove, Jie Gu
A Wearable Bio-signal Processing System with Ultra-low-power SoC and Collaborative Neural Network Classifier for Low Dimensional Data Communication. EMBC (2020)
Tianyu Jia, Yuhao Ju, Jie Gu
31.3 A Compute-Adaptive Elastic Clock-Chain Technique with Dynamic Timing Enhancement for 2D PE-Array-Based Accelerators. ISSCC (2020)
Yijie Wei, Kofi Otseidu, Jie Gu
Exploration of Design Space and Runtime Optimization for Affective Computing in Machine Learning Empowered Ultra-Low Power SoC. DAC (2020)
Tianyu Jia, Yuhao Ju, Russ Joseph, Jie Gu
NCPU: An Embedded Neural CPU Architecture on Resource-Constrained Low Power Devices for Real-time End-to-End Performance. MICRO (2020)
Tianyu Jia, Yijie Wei, Russ Joseph, Jie Gu
An Adaptive Clock Scheme Exploiting Instruction-Based Dynamic Timing Slack for a GPGPU Architecture. IEEE J. Solid State Circuits 55 (8) (2020)
Yijie Wei, Qiankai Cao, Jie Gu, Kofi Otseidu, Levi J. Hargrove
A Fully-integrated Gesture and Gait Processing SoC for Rehabilitation with ADC-less Mixed-signal Feature Extraction and Deep Neural Network for Classification and Online Training. CICC (2020)
Zhengyu Chen, Sihua Fu, Qiankai Cao, Jie Gu
A Mixed-Signal Time-Domain Generative Adversarial Network Accelerator with Efficient Subthreshold Time Multiplier and Mixed-Signal On-Chip Training for Low Power Edge Devices. VLSI Circuits (2020)
Zhengyu Chen, Jie Gu
A Scalable Pipelined Time-Domain DTW Engine for Time-Series Classification Using Multibit Time Flip-Flops With 140Giga-Cell-Updates/s Throughput. ISSCC (2019)
Tianyu Jia, Russ Joseph, Jie Gu
An Adaptive Clock Management Scheme Exploiting Instruction-Based Dynamic Timing Slack for a General-Purpose Graphics Processor Unit with Deep Pipeline and Out-of-Order Execution. ISSCC (2019)
Zhengyu Chen, Jie Gu
A Time-Domain Computing Accelerated Image Recognition Processor With Efficient Time Encoding and Non-Linear Logic Operation. IEEE J. Solid State Circuits 54 (11) (2019)
Tianyu Jia, Russ Joseph, Jie Gu
An Instruction-Driven Adaptive Clock Management Through Dynamic Phase Scaling and Compiler Assistance for a Low Power Microprocessor. IEEE J. Solid State Circuits 54 (8) (2019)
Zhengyu Chen, Hai Zhou, Jie Gu
Digital Compatible Synthesis, Placement and Implementation of Mixed-Signal Time-Domain Computing. DAC (2019)
Zhengyu Chen, Hai Zhou, Jie Gu
R-Accelerator: An RRAM-Based CGRA Accelerator With Logic Contraction. IEEE Trans. Very Large Scale Integr. Syst. 27 (11) (2019)
Amin Rezaei, Jie Gu, Hi Zhou
Hybrid Memristor-CMOS Obfuscation Against Untrusted Foundries. ISVLSI (2019)
Zhengyu Chen, Huanyu Wang, Geng Xie, Jie Gu
A Comprehensive Stochastic Design Methodology for Hold-Timing Resiliency in Voltage-Scalable Design. IEEE Trans. Very Large Scale Integr. Syst. 26 (10) (2018)
Amin Rezaei, Yuanqi Shen, Shuyu Kong, Jie Gu, Hai Zhou
Cyclic locking and memristor-based obfuscation against CycSAT and inside foundry attacks. DATE (2018)
Tianyu Jia, Russ Joseph, Jie Gu
An Instruction Driven Adaptive Clock Phase Scaling with Timing Encoding and Online Instruction Calibration for a Low Power Microprocessor. ESSCIRC (2018)
Tianyu Jia, Jie Gu
A Fully Integrated Buck Regulator With 2-GHz Resonant Switching for Low-Power Applications. IEEE J. Solid State Circuits 53 (9) (2018)
Zhengyu Chen, Hai Zhou, Jie Gu
R-Accelerator: A Reconfigurable Accelerator with RRAM Based Logic Contraction and Resource Optimization for Application Specific Computing. ICCD (2018)
Josiah D. Hester, Tianyu Jia, Jie Gu
Holistic Energy Management with μProcessor Co-Optimization in Fully Integrated Battery-Less IoTs. SoCC (2018)
Yuanbo Fan, Tianyu Jia, Jie Gu, Simone Campanoni, Russ Joseph
Compiler-guided instruction-level clock scheduling for timing speculative processors. DAC (2018)
Tianyu Jia, Jie Gu
A Fully-integrated LC-Oscillator Based Buck Regulator with Autonomous Resonant Switching for Low-Power Applications. A-SSCC (2018)
Zhengyu Chen, Jie Gu
An Image Recognition Processor with Time-domain Accelerators using Efficient Time Encoding and Non-linear Logic Operation. A-SSCC (2018)
Shuyu Kong, Hai Zhou, Jie Gu
Design and Synthesis of Self-Healing Memristive Circuits for Timing Resilient Processor Design. IEEE Trans. Very Large Scale Integr. Syst. 26 (12) (2018)
Kofi Otseidu, Tianyu Jia, Joshua Bryne, Levi J. Hargrove, Jie Gu
Design and optimization of edge computing distributed neural processor for biomedical rehabilitation with sensor fusion. ICCAD (2018)
Amin Rezaei, Yuanqi Shen, Shuyu Kong, Jie Gu, Hai Zhou
Cyclic Locking and Memristor-based Obfuscation Against CycSAT and Inside Foundry Attacks. IACR Cryptol. ePrint Arch. 2017 (2017)
Tianyu Jia, Yuanbo Fan, Russ Joseph, Jie Gu
(Invited) Software-guided greybox design methodology with integrated power and clock management. MWSCAS (2017)
Shuyu Kong, Jie Gu, Hai Zhou
Memristor-Based Clock Design and Optimization with In-Situ Tunability. ISVLSI (2017)
Tianyu Jia, Russ Joseph, Jie Gu
Greybox Design Methodology: A Program Driven Hardware Co-optimization with Ultra-Dynamic Clock Management. DAC (2017)
Zhengyu Chen, Jie Gu
Analysis and Design of Energy Efficient Time Domain Signal Processing. ISLPED (2016)
Tianyu Jia, Yuanbo Fan, Russ Joseph, Jie Gu
Exploration of associative power management with instruction governed operation for ultra-low power design. DAC (2016)
Huanyu Wang, Geng Xie, Jie Gu
Comprehensive Analysis, Modeling and Design for Hold-Timing Resiliency in Voltage Scalable Design. ISLPED (2016)