15.3 A 65nm 3T Dynamic Analog RAM-Based Computing-in-Memory Macro and CNN Accelerator with Retention Enhancement, Adaptive Analog Sparsity and 44TOPS/W System Energy Efficiency.
Zhengyu ChenXi ChenJie GuPublished in: ISSCC (2021)
Keyphrases
- energy efficiency
- energy consumption
- power consumption
- sensor networks
- energy efficient
- wireless sensor networks
- data center
- power management
- routing protocol
- main memory
- energy saving
- floating gate
- energy conservation
- response time
- energy management
- artificial intelligence
- sensor nodes
- high performance computing
- wireless sensor
- low power
- cellular neural networks
- power saving
- traffic load
- battery powered
- database