Timed Test Generation Crosstalk Switch Failures in Domino CMOS Circuits.
Rahul KunduR. D. (Shawn) BlantonPublished in: VTS (2002)
Keyphrases
- test generation
- high speed
- delay insensitive
- analog vlsi
- circuit design
- test cases
- low power
- cmos technology
- symbolic execution
- vlsi circuits
- test sequences
- petri net
- design automation
- focal plane
- static analysis
- quality assurance
- software testing
- power dissipation
- floating gate
- random access memory
- low voltage
- mutation testing
- power consumption
- chip design
- asynchronous circuits
- data model
- test data generation
- source code
- low cost
- multi agent systems
- video sequences
- image processing
- real world