Eriko Nurvitadhi

Publication Activity (10 Years)

Years Active: 2003-2024
Publications (10 Years): 58

Top Topics

High Throughput

Matrix Multiplication

Top Venues

Publications

Anupreetham Anupreetham, Mohamed Ibrahim, Mathew Hall, Andrew Boutros, Ajay Kuzhively, Abinash Mohanty, Eriko Nurvitadhi, Vaughn Betz, Yu Cao, Jae-Sun Seo
High Throughput FPGA-Based Object Detection via Algorithm-Hardware Co-Design. ACM Trans. Reconfigurable Technol. Syst. 17 (1) (2024)
Andrew Boutros, Eriko Nurvitadhi, Vaughn Betz
RAD-Sim: Rapid Architecture Exploration for Novel Reconfigurable Acceleration Devices. CoRR (2023)
Zhiqiang Que, Hiroki Nakahara, Hongxiang Fan, He Li, Jiuxi Meng, Kuen Hung Tsoi, Xinyu Niu, Eriko Nurvitadhi, Wayne Luk
Remarn: A Reconfigurable Multi-threaded Multi-core Accelerator for Recurrent Neural Networks. ACM Trans. Reconfigurable Technol. Syst. 16 (1) (2023)
Suyeon Hur, Seongmin Na, Dongup Kwon, Joonsung Kim, Andrew Boutros, Eriko Nurvitadhi, Jangwoo Kim
A Fast and Flexible FPGA-based Accelerator for Natural Language Processing Neural Networks. ACM Trans. Archit. Code Optim. 20 (1) (2023)
Zhipeng Zhao, Joseph Melber, Siddharth Sahay, Shashank Obla, Eriko Nurvitadhi, James C. Hoe
Exploiting the Common Case When Accelerating Input-Dependent Stream Processing by FPGA. IEEE Trans. Computers 72 (5) (2023)
Zhiqiang Que, Hiroki Nakahara, Eriko Nurvitadhi, Andrew Boutros, Hongxiang Fan, Chenglong Zeng, Jiuxi Meng, Kuen Hung Tsoi, Xinyu Niu, Wayne Luk
Recurrent Neural Networks With Column-Wise Matrix-Vector Multiplication on FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 30 (2) (2022)
Andrew Boutros, Eriko Nurvitadhi, Vaughn Betz
Architecture and Application Co-Design for Beyond-FPGA Reconfigurable Acceleration Devices. IEEE Access 10 (2022)
Adel Ejjeh, Leon Medvinsky, Aaron Councilman, Hemang Nehra, Suraj Sharma, Vikram S. Adve, Luigi Nardi, Eriko Nurvitadhi, Rob A. Rutenbar
HPVM2FPGA: Enabling True Hardware-Agnostic FPGA Programming. ASAP (2022)
Andrew Boutros, Eriko Nurvitadhi, Vaughn Betz
RAD-Sim: Rapid Architecture Exploration for Novel Reconfigurable Acceleration Devices. FPL (2022)
Rui Ma, Evangelos Georganas, Alexander Heinecke, Sergey Gribok, Andrew Boutros, Eriko Nurvitadhi
FPGA-Based AI Smart NICs for Scalable Distributed AI Training Systems. IEEE Comput. Archit. Lett. 21 (2) (2022)
Rui Ma, Evangelos Georganas, Alexander Heinecke, Andrew Boutros, Eriko Nurvitadhi
FPGA-based AI Smart NICs for Scalable Distributed AI Training Systems. CoRR (2022)
Martin Langhammer, Eriko Nurvitadhi, Sergey Gribok, Bogdan Pasca
Stratix 10 NX Architecture. ACM Trans. Reconfigurable Technol. Syst. 15 (4) (2022)
Xiaowei Wang, Vidushi Goyal, Jiecao Yu, Valeria Bertacco, Andrew Boutros, Eriko Nurvitadhi, Charles Augustine, Ravi R. Iyer, Reetuparna Das
Compute-Capable Block RAMs for Efficient Deep Learning Acceleration on FPGAs. FCCM (2021)
Xiaowei Wang, Charles Augustine, Eriko Nurvitadhi, Ravi Iyer, Li Zhao, Reetuparna Das
Cache Compression with Efficient in-SRAM Data Comparison. NAS (2021)
Anupreetham Anupreetham, Mohamed Ibrahim, Mathew Hall, Andrew Boutros, Ajay Kuzhively, Abinash Mohanty, Eriko Nurvitadhi, Vaughn Betz, Yu Cao, Jae-sun Seo
End-to-End FPGA-based Object Detection Using Pipelined CNN and Non-Maximum Suppression. FPL (2021)
Martin Langhammer, Eriko Nurvitadhi, Bogdan Pasca, Sergey Gribok
Stratix 10 NX Architecture and Applications. FPGA (2021)
Rui Ma, Jia-Ching Hsu, Tian Tan, Eriko Nurvitadhi, David Sheffield, Rob Pelt, Martin Langhammer, Jaewoong Sim, Aravind Dasu, Derek Chiou
Specializing FGPU for Persistent Deep Learning. ACM Trans. Reconfigurable Technol. Syst. 14 (2) (2021)
Jessica Vandebon, José Gabriel de Figueiredo Coutinho, Wayne Luk, Eriko Nurvitadhi
Enhancing High-Level Synthesis Using a Meta-Programming Approach. IEEE Trans. Computers 70 (12) (2021)
Rui Ma, Jia-Ching Hsu, Tian Tan, Eriko Nurvitadhi, Rajesh Vivekanandham, Aravind Dasu, Martin Langhammer, Derek Chiou
DO-GPU: Domain Optimizable Soft GPUs. FPL (2021)
Tian Tan, Eriko Nurvitadhi, Aravind Dasu, Martin Langhammer, Derek Chiou
FlexScore: Quantifying Flexibility. IEEE Comput. Archit. Lett. 20 (1) (2021)
Andrew Boutros, Eriko Nurvitadhi, Vaughn Betz
Specializing for Efficiency: Customizing AI Inference Processors on FPGAs. ICM (2021)
Jessica Vandebon, José Gabriel F. Coutinho, Wayne Luk, Eriko Nurvitadhi, Tim Todman
Artisan: a Meta-Programming Approach For Codifying Optimisation Strategies. FCCM (2020)
Shreyas K. Venkataramanaiah, Han-Sok Suh, Shihui Yin, Eriko Nurvitadhi, Aravind Dasu, Yu Cao, Jae-Sun Seo
FPGA-based Low-Batch Training Accelerator for Modern CNNs Featuring High Bandwidth Memory. ICCAD (2020)
Zhiqiang Que, Hiroki Nakahara, Hongxiang Fan, Jiuxi Meng, Kuen Hung Tsoi, Xinyu Niu, Eriko Nurvitadhi, Wayne Luk
A Reconfigurable Multithreaded Accelerator for Recurrent Neural Networks. FPT (2020)
Dongup Kwon, Suyeon Hur, Hamin Jang, Eriko Nurvitadhi, Jangwoo Kim
Scalable Multi-FPGA Acceleration for Large RNNs with Full Parallelism Levels. DAC (2020)
Andrew Boutros, Eriko Nurvitadhi, Rui Ma, Sergey Gribok, Zhipeng Zhao, James C. Hoe, Vaughn Betz, Martin Langhammer
Beyond Peak Performance: Comparing the Real Performance of AI-Optimized FPGAs and GPUs. FPT (2020)
Jessica Vandebon, José Gabriel F. Coutinho, Wayne Luk, Eriko Nurvitadhi, Mishali Naik
SLATE: Managing Heterogeneous Cloud Functions. ASAP (2020)
Zhiqiang Que, Hiroki Nakahara, Eriko Nurvitadhi, Hongxiang Fan, Chenglong Zeng, Jiuxi Meng, Xinyu Niu, Wayne Luk
Optimizing Reconfigurable Recurrent Neural Networks. FCCM (2020)
Yu Wang, James C. Hoe, Eriko Nurvitadhi
Processor Assisted Worklist Scheduling for FPGA Accelerated Graph Processing on a Shared-Memory Platform. FCCM (2019)
Eriko Nurvitadhi, Dongup Kwon, Ali Jafari, Andrew Boutros, Jaewoong Sim, Phillip Tomson, Huseyin Sumbul, Gregory K. Chen, Phil V. Knag, Raghavan Kumar, Ram Krishnamurthy, Sergey Gribok, Bogdan Pasca, Martin Langhammer, Debbie Marr, Aravind Dasu
Why Compete When You Can Work Together: FPGA-ASIC Integration for Persistent RNNs. FCCM (2019)
Shreyas Kolala Venkataramanaiah, Yufei Ma, Shihui Yin, Eriko Nurvitadhi, Aravind Dasu, Yu Cao, Jae-sun Seo
Automatic Compiler Based FPGA Accelerator for CNN Training. FPL (2019)
Jessica Vandebon, José Gabriel F. Coutinho, Wayne Luk, Eriko Nurvitadhi, Mishali Naik
Enhanced Heterogeneous Cloud: Transparent Acceleration and Elasticity. FPT (2019)
Eriko Nurvitadhi, Dongup Kwon, Ali Jafari, Andrew Boutros, Jaewoong Sim, Phillip Tomson, Huseyin Sumbul, Gregory K. Chen, Phil V. Knag, Raghavan Kumar, Ram Krishnamurthy, Debbie Marr, Sergey Gribok, Bogdan Pasca, Martin Langhammer, Aravind Dasu
Evaluating and Enhancing Intel® Stratix® 10 FPGAs for Persistent Real-Time AI. FPGA (2019)
Tian Tan, Eriko Nurvitadhi, Derek Chiou
Dark Wires and the Opportunities for Reconfigurable Logic. IEEE Comput. Archit. Lett. 18 (1) (2019)
Eriko Nurvitadhi, Mishali Naik, Andrew Boutros, Prerna Budhkar, Ali Jafari, Dongup Kwon, David Sheffield, Abirami Prabhakaran, Karthik Gururaj, Pranavi Appana
Scalable Low-Latency Persistent Neural Machine Translation on CPU Server with Multiple FPGAs. FPT (2019)
Shreyas Kolala Venkataramanaiah, Yufei Ma, Shihui Yin, Eriko Nurvitadhi, Aravind Dasu, Yu Cao, Jae-sun Seo
Automatic Compiler Based FPGA Accelerator for CNN Training. CoRR (2019)
Rui Ma, Derek Chiou, Jia-Ching Hsu, Tian Tan, Eriko Nurvitadhi, David Sheffield, Rob Pelt, Martin Langhammer, Jaewoong Sim, Aravind Dasu
Specializing FGPU for Persistent Deep Learning. FPL (2019)
Eriko Nurvitadhi
FPGA-based Computing in the Era of AI and Big Data. ISPD (2019)
Tian Tan, Eriko Nurvitadhi, David Shih, Derek Chiou
Evaluating The Highly-Pipelined Intel Stratix 10 FPGA Architecture Using Open-Source Benchmarks. FPT (2018)
Philip Colangelo, Nasibeh Nasiri, Eriko Nurvitadhi, Asit K. Mishra, Martin Margala, Kevin Nealis
Exploration of Low Numeric Precision Deep Learning Inference Using Intel® FPGAs. FCCM (2018)
Eriko Nurvitadhi, Jeffrey J. Cook, Asit K. Mishra, Debbie Marr, Kevin Nealis, Philip Colangelo, Andrew C. Ling, Davor Capalija, Utku Aydonat, Sergey Y. Shumarayev, Aravind Dasu
In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC(Abstract Only). FPGA (2018)
Philip Colangelo, Nasibeh Nasiri, Asit K. Mishra, Eriko Nurvitadhi, Martin Margala, Kevin Nealis
Exploration of Low Numeric Precision Deep Learning Inference Using Intel FPGAs. CoRR (2018)
Duncan J. M. Moss, Krishnan Srivatsan, Eriko Nurvitadhi, Piotr Ratuszniak, Chris Johnson, Jaewoong Sim, Asit K. Mishra, Debbie Marr, Suchit Subhaschandra, Philip Heng Wai Leong
A Customizable Matrix Multiplication Framework for the Intel HARPv2 Xeon+FPGA Platform: A Deep Learning Case Study. FPGA (2018)
Asit K. Mishra, Eriko Nurvitadhi, Jeffrey J. Cook, Debbie Marr
WRPN: Wide Reduced-Precision Networks. ICLR (Poster) (2018)
Philip Colangelo, Nasibeh Nasiri, Eriko Nurvitadhi, Asit K. Mishra, Martin Margala, Kevin Nealis
Exploration of Low Numeric Precision Deep Learning Inference Using Intel® FPGAs: (Abstract Only). FPGA (2018)
Eriko Nurvitadhi, Jeffrey J. Cook, Asit K. Mishra, Debbie Marr, Kevin Nealis, Philip Colangelo, Andrew C. Ling, Davor Capalija, Utku Aydonat, Aravind Dasu, Sergey Y. Shumarayev
In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC. FPL (2018)
Asit K. Mishra, Eriko Nurvitadhi, Ganesh Venkatesh, Jonathan Pearce, Debbie Marr
Fine-grained accelerators for sparse machine learning workloads. ASP-DAC (2017)
Asit K. Mishra, Jeffrey J. Cook, Eriko Nurvitadhi, Debbie Marr
WRPN: Training and Inference using Wide Reduced-Precision Networks. CoRR (2017)
Duncan J. M. Moss, Eriko Nurvitadhi, Jaewoong Sim, Asit K. Mishra, Debbie Marr, Suchit Subhaschandra, Philip Heng Wai Leong
High performance binary neural networks on the Xeon+FPGA™ platform. FPL (2017)
Ganesh Venkatesh, Eriko Nurvitadhi, Debbie Marr
Accelerating Deep Convolutional Networks using low-precision and sparsity. ICASSP (2017)
Eriko Nurvitadhi, Ganesh Venkatesh, Jaewoong Sim, Debbie Marr, Randy Huang, Jason Ong Gee Hock, Yeong Tat Liew, Krishnan Srivatsan, Duncan J. M. Moss, Suchit Subhaschandra, Guy Boudoukh
Can FPGAs Beat GPUs in Accelerating Next-Generation Deep Neural Networks? FPGA (2017)
Asit K. Mishra, Eriko Nurvitadhi, Jeffrey J. Cook, Debbie Marr
WRPN: Wide Reduced-Precision Networks. CoRR (2017)
Jack Yinger, Eriko Nurvitadhi, Davor Capalija, Andrew C. Ling, Debbie Marr, Krishnan Srivatsan, Duncan J. M. Moss, Suchit Subhaschandra
Customizable FPGA OpenCL matrix multiply design template for deep neural networks. FPT (2017)
Eriko Nurvitadhi, David Sheffield, Jaewoong Sim, Asit K. Mishra, Ganesh Venkatesh, Debbie Marr
Accelerating Binarized Neural Networks: Comparison of FPGA, CPU, GPU, and ASIC. FPT (2016)
Gabriel Weisz, Joseph Melber, Yu Wang, Kermin Fleming, Eriko Nurvitadhi, James C. Hoe
A Study of Pointer-Chasing Performance on Shared-Memory Processor-FPGA Systems. FPGA (2016)
Ganesh Venkatesh, Eriko Nurvitadhi, Debbie Marr
Accelerating Deep Convolutional Networks using low-precision and sparsity. CoRR (2016)
Eriko Nurvitadhi, Jaewoong Sim, David Sheffield, Asit K. Mishra, Krishnan Srivatsan, Debbie Marr
Accelerating recurrent neural networks in analytics servers: Comparison of FPGA, CPU, GPU, and ASIC. FPL (2016)
Eriko Nurvitadhi, Asit K. Mishra, Yu Wang, Ganesh Venkatesh, Debbie Marr
Hardware accelerator for analytics of sparse data. DATE (2016)
Skand Hurkat, Jungwook Choi, Eriko Nurvitadhi, José F. Martínez, Rob A. Rutenbar
Fast hierarchical implementation of sequential tree-reweighted belief propagation for probabilistic inference. FPL (2015)
Eriko Nurvitadhi, Asit K. Mishra, Debbie Marr
A sparse matrix vector multiply accelerator for support vector machine. CASES (2015)
Robert Tamburo, Eriko Nurvitadhi, Abhishek Chugh, Mei Chen, Anthony Rowe, Takeo Kanade, Srinivasa G. Narasimhan
Programmable Automotive Headlights. ECCV (4) (2014)
Eriko Nurvitadhi, Gabriel Weisz, Yu Wang, Skand Hurkat, Marie Nguyen, James C. Hoe, José F. Martínez, Carlos Guestrin
GraphGen: An FPGA Framework for Vertex-Centric Graph Computation. FCCM (2014)
Eriko Nurvitadhi
MEMOCODE 2013 hardware/software co-design contest: Stereo matching. MEMOCODE (2013)
Abhishek A. Sharma, Kaustubh Neelathalli, Diana Marculescu, Eriko Nurvitadhi
Hardware-efficient stereo estimation using a residual-based approach. ICASSP (2013)
Hyun Soo Park, Yu Wang, Eriko Nurvitadhi, James C. Hoe, Yaser Sheikh, Mei Chen
3D Point Cloud Reduction Using Mixed-Integer Quadratic Programming. CVPR Workshops (2013)
Eriko Nurvitadhi, James C. Hoe, Timothy Kam, Shih-Lien Lu
Automatic Pipelining From Transactional Datapath Specifications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30 (3) (2011)
Eriko Nurvitadhi, James C. Hoe, Timothy Kam, Shih-Lien Lu
Integrating formal verification and high-level processor pipeline synthesis. SASP (2011)
Eriko Nurvitadhi, James C. Hoe, Timothy Kam, Shih-Lien Lu
Automatic pipelining from transactional datapath specifications. DATE (2010)
Eriko Nurvitadhi, James C. Hoe, Shih-Lien Lu, Timothy Kam
Automatic multithreaded pipeline synthesis from transactional datapath specifications. DAC (2010)
Eric S. Chung, Michael Papamichael, Eriko Nurvitadhi, James C. Hoe, Ken Mai, Babak Falsafi
ProtoFlex: Towards Scalable, Full-System Multiprocessor Simulations Using FPGAs. ACM Trans. Reconfigurable Technol. Syst. 2 (2) (2009)
Eriko Nurvitadhi, Jumnit Hong, Shih-Lien Lu
Active Cache Emulator. IEEE Trans. Very Large Scale Integr. Syst. 16 (3) (2008)
Eric S. Chung, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi, Ken Mai
A complexity-effective architecture for accelerating full-system multiprocessor simulations using FPGAs. FPGA (2008)
Eric S. Chung, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi, Ken Mai
PROToFLEX: FPGA-accelerated Hybrid Functional Simulator. IPDPS (2007)
Eriko Nurvitadhi, Ben Lee, Chansu Yu, Myungchul Kim
Adaptive semi-soft handoff for Cellular IP networks. Int. J. Wirel. Mob. Comput. 2 (2/3) (2007)
Jumnit Hong, Eriko Nurvitadhi, Shih-Lien Lu
Design, implementation, and verification of active cache emulator (ACE). FPGA (2006)
Brian T. Gold, Jangwoo Kim, Jared C. Smolens, Eric S. Chung, Vasileios Liaskovitis, Eriko Nurvitadhi, Babak Falsafi, James C. Hoe, Andreas Nowatzyk
TRUSS: A Reliable, Scalable Server Architecture. IEEE Micro 25 (6) (2005)
Eriko Nurvitadhi, Nirut Chalainanont, Shih-Lien Lu
Characterization of L3 cache behavior of SPECjAppServer2002 and TPC-C. ICS (2005)
Ben Lee, Eriko Nurvitadhi, Reshma Dixit, Chansu Yu, Myungchul Kim
Dynamic voltage scaling techniques for power efficient video decoding. J. Syst. Archit. 51 (10-11) (2005)
Eriko Nurvitadhi, Ben Lee, Chansu Yu, Myungchul Kim
A Comparative Study of Dynamic Voltage Scaling Techniques for Low-Power Video Decoding. Embedded Systems and Applications (2003)